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Publication numberUSD427088 S
Publication typeGrant
Application numberUS 29/114,644
Publication dateJun 27, 2000
Filing dateNov 29, 1999
Priority dateJul 9, 1999
Publication number114644, 29114644, US D427088 S, US D427088S, US-S-D427088, USD427088 S, USD427088S
InventorsYoshihiko Asai, Yoshikazu Ezawa
Original AssigneeMatsushita Electric Industrial Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Wafer level burn-in tester
US D427088 S
Abstract  available in
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  1. The ornamental design for a wafer level burn-in tester, as shown and described.

FIG. 1 is a perspective view of the top, front and right side of a wafer level burn-in tester showing our new design;

FIG. 2 is a front view thereof;

FIG. 3 is a right side view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom view thereof; and,

FIG. 6 is a rear view thereof.

U.S. ClassificationD10/75