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Publication numberUSD459317 S1
Publication typeGrant
Application numberUS 29/144,821
Publication dateJun 25, 2002
Filing dateJul 12, 2001
Priority dateFeb 15, 2001
Publication number144821, 29144821, US D459317 S1, US D459317S1, US-S1-D459317, USD459317 S1, USD459317S1
InventorsTakakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura
Original AssigneeMitsubishi Denki Kabushiki Kaisha
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device
US D459317 S1
Images(5)
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Claims(1)
  1. The ornamental design for a semiconductor device, as shown and described.
Description

FIG. 1 is a front, top and right side perspective view of a semiconductor device, showing our new design;

FIG. 2 is a front, bottom and right side perspective view thereof;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a rear elevational view thereof;

FIG. 5 is a right side elevational view thereof; the left side elevational view is omitted as that is symmetrical to the right side elevational view thereof;

FIG. 6 is a top plan view thereof;

FIG. 7 is a bottom plan view thereof; and,

FIG. 8 is a cross-sectional view thereof, taken along line 88 of FIG. 5, with the internal system omitted.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6686654 *Aug 31, 2001Feb 3, 2004Micron Technology, Inc.Multiple chip stack structure and cooling system
US6861287Sep 15, 2003Mar 1, 2005Micron Technology, Inc.Multiple chip stack structure and cooling system
US6975027May 7, 2004Dec 13, 2005Micron Technology, Inc.Multi-chip electronic package and cooling system
US7465608Aug 17, 2004Dec 16, 2008Micron Technology, Inc.Three-dimensional multichip module
US7626252Dec 13, 2005Dec 1, 2009Micron Technology, Inc.Multi-chip electronic package and cooling system
Classifications
U.S. ClassificationD13/182