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Publication numberUSD459705 S1
Publication typeGrant
Application numberUS 29/142,698
Publication dateJul 2, 2002
Filing dateJun 1, 2001
Priority dateMar 6, 2001
Publication number142698, 29142698, US D459705 S1, US D459705S1, US-S1-D459705, USD459705 S1, USD459705S1
InventorsYoshio Yokota, Nobuyuki Yokote
Original AssigneeShindengen Electric Manufacturing Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor package
US D459705 S1
Abstract  available in
Images(3)
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Claims(1)
  1. The ornamental design for a semiconductor package, as shown and described.
Description

FIG. 1 is a front, plan and right side perspective view of a semiconductor package showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a left side elevational view thereof; and,

FIG. 7 is a right side elevational view thereof.

The broken lines are shown in the views for illustrative purposes only and form no part of the claimed design.

Non-Patent Citations
Reference
1Japanese Design Application No. 929231, Publication Date: Jul. 6, 1995.
2Japanese Design Application No. 982886, Publication Date: Jun. 17, 1997.
3Japanese Design Application No. 982886—Similar 1, Publication Date: Jun. 24, 1997.
Classifications
U.S. ClassificationD13/182