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Publication numberUSD466485 S1
Publication typeGrant
Application numberUS 29/142,263
Publication dateDec 3, 2002
Filing dateMay 23, 2001
Priority dateMay 23, 2001
Publication number142263, 29142263, US D466485 S1, US D466485S1, US-S1-D466485, USD466485 S1, USD466485S1
InventorsKenichi Maehara, Koji Igarashi
Original AssigneeShindengen Electric Manufactuturing Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor package
US D466485 S1
Images(5)
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Claims(1)
  1. The ornamental design for a semiconductor package, as shown and described.
Description

FIG. 1 is a front, plan and right side perspective view of a semiconductor package showing our new design;

FIG. 2 is a front, bottom and right side perspective view thereof;

FIG. 3 is a rear, plan and left side perspective view thereof;

FIG. 4 is a rear, bottom and left side perspective view thereof;

FIG. 5 is a front elevational view thereof;

FIG. 6 is a rear elevational view thereof;

FIG. 7 is a top plan view thereof;

FIG. 8 is a bottom plan view thereof;

FIG. 9 is a left side elevational view thereof; and,

FIG. 10 is a right side elevational view thereof.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8638535 *Jan 10, 2011Jan 28, 2014Hamilton Sundstrand CorporationVertical mount transient voltage suppressor array
US20120176716 *Jan 10, 2011Jul 12, 2012Hamilton Sundstrand CorporationVertical mount transient voltage suppressor array
Classifications
U.S. ClassificationD13/182