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Publication numberUSD471165 S1
Publication typeGrant
Application numberUS 29/141,963
Publication dateMar 4, 2003
Filing dateMay 15, 2001
Priority dateMay 15, 2001
Publication number141963, 29141963, US D471165 S1, US D471165S1, US-S1-D471165, USD471165 S1, USD471165S1
InventorsRichard K. Williams, James Harnden, Anthony Chia, Chu Weibing
Original AssigneeGem Services, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Surface mount package
US D471165 S1
Abstract  available in
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  1. The ornamental design for a surface mount package, as shown and described.

FIG. 1 is a perspective view of a surface mount package showing our new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a bottom plan view thereof;

FIG. 4 is a front elevational view thereof:

FIG. 5 is a rear elevational view thereof;

FIG. 6 is a left side elevational view thereof; and,

FIG. 7 the right side elevational view thereof.

The broken line showing of the environment is for illustrative purpose only and forms no part of the claimed design.

Non-Patent Citations
1JEDEC Solid State Product Outline, Low Profile Small Outline J-Lead Package (LSOJ), PRSO-J/LSOJ, Issue B, Jun., 1999, MO-199, pp. 1-5.
2JEDEC Solid State Product Outlines, "Plastic Small Outline (SOJ) Package Family with .330 Inch Body Width", Issue B, May, 1992, MO-121, pp. 1-2.
3JEDEC Solid State Product Outlines, "Small Outline J-Lead" (SOJ) .300 Body Family (MS-013 Body), Issue A, Jun., 1988, MO-088, AA-AF.
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US7446375Mar 14, 2006Nov 4, 2008Ciclon Semiconductor Device Corp.Quasi-vertical LDMOS device having closed cell layout
US7504733Aug 17, 2005Mar 17, 2009Ciclon Semiconductor Device Corp.Semiconductor die package
US7560808Jul 14, 2009Texas Instruments IncorporatedChip scale power LDMOS device
US8049312Nov 1, 2011Texas Instruments IncorporatedSemiconductor device package and method of assembly thereof
US8304903Dec 13, 2010Nov 6, 2012Texas Instruments IncorporatedWirebond-less semiconductor package
US20070040254 *Aug 17, 2005Feb 22, 2007Lopez Osvaldo JSemiconductor die package
US20070085204 *Oct 19, 2005Apr 19, 2007Cicion Semiconductor Device Corp.Chip scale power LDMOS device
U.S. ClassificationD13/182