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Publication numberUSD471524 S1
Publication typeGrant
Application numberUS 29/158,473
Publication dateMar 11, 2003
Filing dateApr 5, 2002
Priority dateApr 27, 2001
Also published asUSD459706
Publication number158473, 29158473, US D471524 S1, US D471524S1, US-S1-D471524, USD471524 S1, USD471524S1
InventorsHitoshi Ebihara, Naoki Tomaru, Yoshiyuki Wasada, Tetsuya Ito, Hideki Kato, Tomohiro Igarashi, Hideki Yoda
Original AssigneeTaiyo Yuden Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Hybrid integrated circuit device
US D471524 S1
Abstract  available in
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  1. The ornamental design for a hybrid integrated circuit device, as shown and described.

FIG. 1 is a perspective view of a hybrid integrated circuit device showing an embodiment of our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a right side elevational view thereof;

FIG. 6 is a top plan view thereof; and,

FIG. 7 is a bottom plan view thereof.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
USD731990 *Oct 17, 2012Jun 16, 2015Nok CorporationIntegrated circuit tag
USD740239 *May 7, 2014Oct 6, 2015Bejan Esau AminiLED illumination tile
USD745476 *Feb 27, 2013Dec 15, 2015Solumatics CVBAPrint board
USD753073 *Dec 30, 2014Apr 5, 2016Altia Systems, Inc.Printed circuit board
USD757666 *Apr 1, 2015May 31, 2016Japan Aviation Electronics Industry, LimitedFlexible printed circuit
USD764424Aug 29, 2014Aug 23, 2016Kabushiki Kaisha ToshibaSubstrate for an electronic circuit
U.S. ClassificationD13/182