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Publication numberUSD471524 S1
Publication typeGrant
Application numberUS 29/158,473
Publication dateMar 11, 2003
Filing dateApr 5, 2002
Priority dateApr 27, 2001
Also published asUSD459706
Publication number158473, 29158473, US D471524 S1, US D471524S1, US-S1-D471524, USD471524 S1, USD471524S1
InventorsHitoshi Ebihara, Naoki Tomaru, Yoshiyuki Wasada, Tetsuya Ito, Hideki Kato, Tomohiro Igarashi, Hideki Yoda
Original AssigneeTaiyo Yuden Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Hybrid integrated circuit device
US D471524 S1
Images(4)
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Claims(1)
  1. The ornamental design for a hybrid integrated circuit device, as shown and described.
Description

FIG. 1 is a perspective view of a hybrid integrated circuit device showing an embodiment of our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a right side elevational view thereof;

FIG. 6 is a top plan view thereof; and,

FIG. 7 is a bottom plan view thereof.

Classifications
U.S. ClassificationD13/182