US D473198 S1
FIG. 1 is a top plan view of a semiconductor device, showing our new design; a bottom plan view being a mirror image thereof;
FIG. 2 is a right side elevational view thereof; a left side elevational view being a mirror image thereof;
FIG. 3 is a front elevational view thereof; and,
FIG. 4 is a rear elevational view thereof.