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Publication numberUSD475981 S1
Publication typeGrant
Application numberUS 29/165,700
Publication dateJun 17, 2003
Filing dateAug 16, 2002
Priority dateMar 29, 2002
Publication number165700, 29165700, US D475981 S1, US D475981S1, US-S1-D475981, USD475981 S1, USD475981S1
InventorsKazunari Michii
Original AssigneeMitsubishi Denki Kabushiki Kaisha
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integrated circuits substrate
US D475981 S1
Abstract  available in
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  1. The ornamental design for an integrated circuits substrate, as shown and described.

FIG. 1 is a front, top and right side perspective view of an integrated circuits substrate, showing my new design;

FIG. 2 is a front elevational view thereof, the rear elevational view is omitted as that is symmetrical to the front elevational view thereof;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a right side elevational view thereof;

FIG. 6 is a left side elevational view thereof; and,

FIG. 7 is an enlarged cross-sectional view thereof, taken along line 7—7 of FIG. 2, with the internal system omitted.

The broken lines in all views are shown for illustrative purposes only and form no part of the claimed design.

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US8680687Jun 23, 2010Mar 25, 2014Invensas CorporationElectrical interconnect for die stacked in zig-zag configuration
US8704379Aug 27, 2008Apr 22, 2014Invensas CorporationSemiconductor die mount by conformal die coating
US8723332May 20, 2008May 13, 2014Invensas CorporationElectrically interconnected stacked die assemblies
US8742602 *Mar 12, 2008Jun 3, 2014Invensas CorporationVertical electrical interconnect formed on support prior to die mount
US8884403Dec 30, 2010Nov 11, 2014Iinvensas CorporationSemiconductor die array structure
US8912661Nov 4, 2010Dec 16, 2014Invensas CorporationStacked die assembly having reduced stress electrical interconnects
U.S. ClassificationD13/182