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Publication numberUSD476962 S1
Publication typeGrant
Application numberUS 29/168,143
Publication dateJul 8, 2003
Filing dateSep 27, 2002
Priority dateMar 29, 2002
Publication number168143, 29168143, US D476962 S1, US D476962S1, US-S1-D476962, USD476962 S1, USD476962S1
InventorsTakayuki Yoshihira, Gentaro Ookura
Original AssigneeKabushiki Kaisha Toshiba
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device
US D476962 S1
Abstract  available in
Images(5)
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Claims(1)
  1. The ornamental design for a semiconductor device, as shown and described.
Description

FIG. 1 is a front perspective view of a semiconductor device, showing our new design;

FIG. 2 is a rear perspective view thereof;

FIG. 3 is a top plan view thereof; a bottom plan view being a mirror image thereof;

FIG. 4 is a right side elevational view thereof; a left side elevational view being a mirror image thereof;

FIG. 5 is a front elevational view thereof;

FIG. 6 is a rear elevational view thereof;

FIG. 7 is a front perspective view of a second embodiment of a semiconductor device, showing our new design;

FIG. 8 is a rear perspective view thereof;

FIG. 9 is a top plan view thereof; a bottom plan view being a mirror image thereof;

FIG. 10 is a right side elevational view thereof; a left side elevational view being a mirror image thereof;

FIG. 11 is a front elevational view thereof; and,

FIG. 12 is a rear elevational view thereof.

Non-Patent Citations
Reference
1Catalog showing a Power MOSFET (PowerFLAT).
2Website showing a Power MOSFET (P series).
Classifications
U.S. ClassificationD13/182