|Publication number||USD481689 S1|
|Application number||US 29/177,395|
|Publication date||Nov 4, 2003|
|Filing date||Mar 11, 2003|
|Priority date||Mar 6, 2002|
|Publication number||177395, 29177395, US D481689 S1, US D481689S1, US-S1-D481689, USD481689 S1, USD481689S1|
|Original Assignee||Sharp Kabushiki Kaisha|
|Export Citation||BiBTeX, EndNote, RefMan|
|External Links: USPTO, USPTO Assignment, Espacenet|
FIG. 1 is a top, front, and right perspective of a semiconductor device showing my new design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view; and,
FIG. 6 is a right side elevational view, the left side elevational view being a mirror image thereof.
The broken line showing of the environment is for illustrative purpose only and forms no part of the claimed design.