US D487430 S1
FIG. 1 is a top perspective view of a semiconductor memory element showing our new design;
FIG. 2 is a side elevation view thereof, the opposite side view being a mirror image of that shown;
FIG. 3 is a top plan view thereof;
FIG. 4 is a bottom plan view thereof; and,
FIG. 5 is a front elevation view thereof, the rear elevation view being a mirror image of that shown.