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Publication numberUSD487430 S1
Publication typeGrant
Application numberUS 29/171,752
Publication dateMar 9, 2004
Filing dateNov 27, 2002
Priority dateJul 10, 2002
Publication number171752, 29171752, US D487430 S1, US D487430S1, US-S1-D487430, USD487430 S1, USD487430S1
InventorsNobuyoshi Asaka, Takashi Noda, Takao Ochi, Junichi Shinyashiki
Original AssigneeMatsushita Electric Industrial Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor memory element
US D487430 S1
Abstract  available in
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  1. The ornamental design for a semiconductor memory element, as shown and described.

FIG. 1 is a top perspective view of a semiconductor memory element showing our new design;

FIG. 2 is a side elevation view thereof, the opposite side view being a mirror image of that shown;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof; and,

FIG. 5 is a front elevation view thereof, the rear elevation view being a mirror image of that shown.

U.S. ClassificationD13/182, D14/435