|Publication number||USD502151 S1|
|Application number||US 29/189,285|
|Publication date||Feb 22, 2005|
|Filing date||Sep 2, 2003|
|Priority date||Sep 2, 2003|
|Publication number||189285, 29189285, US D502151 S1, US D502151S1, US-S1-D502151, USD502151 S1, USD502151S1|
|Original Assignee||International Rectifier Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Classifications (1) |
|External Links: USPTO, USPTO Assignment, Espacenet|
US D502151 S1
The ornamental design for a semiconductor package, as shown and described.
FIG. 1 is a front elevational view of a semiconductor package, showing our design;
FIG. 2 is a left side elevational view thereof;
FIG. 3 is a top plan view thereof; and,
FIG. 4 is a rear elevational view thereof.
The broken lines shown in the figures are for illustrative purposes only and form no part of the claimed design.