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Publication numberUSD508681 S1
Publication typeGrant
Application numberUS 29/180,814
Publication dateAug 23, 2005
Filing dateMay 1, 2003
Priority dateNov 1, 2002
Publication number180814, 29180814, US D508681 S1, US D508681S1, US-S1-D508681, USD508681 S1, USD508681S1
InventorsJanos-Gerold Enderlein, Jörg Romahn
Original AssigneeSiemens Aktiengesellschaft
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Circuit board
US D508681 S1
Abstract  available in
Images(5)
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Claims(1)
  1. The ornamental design for a circuit board, as shown and described.
Description

FIG. 1 is a front perspective of the invention.

FIG. 2 is a plan elevation of the invention.

FIG. 3 is a bottom plan of the invention.

FIG. 4 is a front elevation of the invention.

FIG. 5 is a rear elevation of the invention.

FIG. 6 is a right end elevation of the invention; and,

FIG. 7 is a left end elevation of the invention.

The broken lines define the boundary of the claimed design and form no part of the claimed design.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
USD769833Aug 29, 2014Oct 25, 2016Apple Inc.Component for electronic device
USD787456Jul 14, 2015May 23, 2017Kabushiki Kaisha ToshibaSubstrate for an electronic circuit
USD794586 *Apr 5, 2016Aug 15, 2017Mitsubishi Electric CorporationCircuit board
USD795823Oct 14, 2016Aug 29, 2017Apple Inc.Component for electronic device
Classifications
U.S. ClassificationD13/182