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Publication numberUSD515520 S1
Publication typeGrant
Application numberUS 29/168,222
Publication dateFeb 21, 2006
Filing dateSep 30, 2002
Priority dateMar 29, 2002
Publication number168222, 29168222, US D515520 S1, US D515520S1, US-S1-D515520, USD515520 S1, USD515520S1
InventorsSatoshi Komoto
Original AssigneeKabushiki Kaisha Toshiba
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device
US D515520 S1
Images(5)
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Claims(1)
  1. The ornamental design for a semiconductor device, as shown and described.
Description

FIG. 1 is a front, top and right side perspective view of a semiconductor device, showing my new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a left side elevational view thereof; and,

FIG. 7 is a right side elevational view thereof.

Non-Patent Citations
Reference
1Extract of Denpa Shimbun (newspaper) showing an insulated gate transistor, Oct. 13, 1998.
Classifications
U.S. ClassificationD13/182
Legal Events
DateCodeEventDescription
Sep 11, 2002ASAssignment
Owner name: COGNIS DEUTSCHLAND GMBH & CO. KG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ANSMANN, ACHIM;EGGERS, ANKE;BRUENING, STEFAN;REEL/FRAME:013078/0020;SIGNING DATES FROM 20020612 TO 20020613