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Publication numberUSD525213 S1
Publication typeGrant
Application numberUS 29/180,813
Publication dateJul 18, 2006
Filing dateMay 1, 2003
Priority dateNov 1, 2002
Publication number180813, 29180813, US D525213 S1, US D525213S1, US-S1-D525213, USD525213 S1, USD525213S1
InventorsJanos-Gerold Enderlein, Jörg Romahn
Original AssigneeSiemens Aktiengesellschaft
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Circuit board
US D525213 S1
Abstract  available in
Images(5)
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Claims(1)
  1. The ornamental design for a circuit board, as shown and described.
Description

FIG. 1 is a front perspective of the invention.

FIG. 2 is a plan elevation of the invention.

FIG. 3 is a bottom plan of the invention.

FIG. 4 is a front elevation of the invention.

FIG. 5 is a rear elevation of the invention.

FIG. 6 is a right end elevation of the invention; and,

FIG. 7 is a left end elevation of the invention.

The broken lines define the boundary of the claimed design and form no part of the claimed design.

Classifications
U.S. ClassificationD13/182