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Publication numberUSD557041 S1
Publication typeGrant
Application numberUS 29/221,166
Publication dateDec 11, 2007
Filing dateJan 11, 2005
Priority dateJan 11, 2005
Fee statusPaid
Also published asCA110905S
Publication number221166, 29221166, US D557041 S1, US D557041S1, US-S1-D557041, USD557041 S1, USD557041S1
InventorsThomas R. Lee, Joseph Thomas Richardson
Original AssigneeBehr Process Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Chips display module
US D557041 S1
Images(4)
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Claims(1)
  1. The ornamental design for a chips display module, as shown and described.
Description

FIG. 1 is a front perspective of the chips display module;

FIG. 2 is a front plan view of the chips display module; and,

FIG. 3 is a left side cross-sectional side view of the chips display module, the right side cross-sectional side view being a mirror image.

The broken lines shown in the drawings are for illustrative purposes only and form no part of the claimed design.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7571823 *Mar 4, 2008Aug 11, 2009Behr Process CorporationIlluminated modular display
US8689493Aug 31, 2011Apr 8, 2014Behr Process CorporationTruss based display system
Classifications
U.S. ClassificationD06/702
Legal Events
DateCodeEventDescription
Apr 14, 2014FPAYFee payment
Year of fee payment: 4
Jan 4, 2011CCCertificate of correction
Dec 29, 2005ASAssignment
Owner name: UNIVERSITY OF MASSACHUSETTS, MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:STEIN, GARY S.;YOUNG, DANIEL W.;ZAIDI, SAYYED K.;AND OTHERS;REEL/FRAME:016953/0884;SIGNING DATES FROM 20051007 TO 20051012
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:STEIN, GARY S.;YOUNG, DANIEL W.;ZAIDI, SAYYED K.;AND OTHERS;SIGNING DATES FROM 20051007 TO 20051012;REEL/FRAME:016953/0884