|Publication number||USD589472 S1|
|Application number||US 29/278,802|
|Publication date||Mar 31, 2009|
|Filing date||Apr 10, 2007|
|Priority date||Oct 10, 2006|
|Publication number||278802, 29278802, US D589472 S1, US D589472S1, US-S1-D589472, USD589472 S1, USD589472S1|
|Original Assignee||Tokyo Electron Limited|
|Export Citation||BiBTeX, EndNote, RefMan|
|Classifications (1) |
|External Links: USPTO, USPTO Assignment, Espacenet|
Processing chamber for manufacturing semiconductors
US D589472 S1
The ornamental design for a processing chamber for manufacturing semiconductors or the like, as shown and described.
FIG. 1 is a top and right front perspective view of a processing chamber for manufacturing semiconductors or the like, showing my new design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a right side elevational view thereof, the left side elevational view being a mirror image of the side view shown;
FIG. 5 is a top plan view thereof;
FIG. 6 is a bottom plan view thereof;
FIG. 7 is a cross-sectional view thereof taken in the direction of the arrows on line 7—7 of FIG. 2; and,
FIG. 8 is a top and right front perspective view thereof in the state of use.
The broken line showing in the figures is for illustrative purposes only and forms no part of the claimed design.