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Publication numberUSD594488 S1
Publication typeGrant
Application numberUS 29/290,024
Publication dateJun 16, 2009
Filing dateOct 12, 2007
Priority dateApr 20, 2007
Publication number290024, 29290024, US D594488 S1, US D594488S1, US-S1-D594488, USD594488 S1, USD594488S1
InventorsMasataka Toiya, Yoshikatsu Mizuno, Hisashi Inoue
Original AssigneeTokyo Electron Limited
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Process tube for manufacturing semiconductor wafers
US D594488 S1
Images(5)
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Claims(1)
  1. The ornamental design for a process tube for manufacturing semiconductor wafers, as shown and described.
Description

FIG. 1 is a front view of the design for a process tube for manufacturing semiconductor wafers in accordance with the invention;

FIG. 2 is a rear view thereof;

FIG. 3 is a right side view thereof;

FIG. 4 is a left side view thereof;

FIG. 5 is a bottom view thereof;

FIG. 6 is a top view thereof; and,

FIG. 7 is a front perspective view thereof.

The broken line showings are for the purpose of illustrating environmental structure and forms no part of the claimed design.

Classifications
U.S. ClassificationD15/144.1, D13/182