|Publication number||USD594488 S1|
|Application number||US 29/290,024|
|Publication date||Jun 16, 2009|
|Filing date||Oct 12, 2007|
|Priority date||Apr 20, 2007|
|Publication number||290024, 29290024, US D594488 S1, US D594488S1, US-S1-D594488, USD594488 S1, USD594488S1|
|Inventors||Masataka Toiya, Yoshikatsu Mizuno, Hisashi Inoue|
|Original Assignee||Tokyo Electron Limited|
|Export Citation||BiBTeX, EndNote, RefMan|
|Classifications (2) |
|External Links: USPTO, USPTO Assignment, Espacenet|
Process tube for manufacturing semiconductor wafers
US D594488 S1
The ornamental design for a process tube for manufacturing semiconductor wafers, as shown and described.
FIG. 1 is a front view of the design for a process tube for manufacturing semiconductor wafers in accordance with the invention;
FIG. 2 is a rear view thereof;
FIG. 3 is a right side view thereof;
FIG. 4 is a left side view thereof;
FIG. 5 is a bottom view thereof;
FIG. 6 is a top view thereof; and,
FIG. 7 is a front perspective view thereof.
The broken line showings are for the purpose of illustrating environmental structure and forms no part of the claimed design.