|Publication number||USD612879 S1|
|Application number||US 29/257,350|
|Publication date||Mar 30, 2010|
|Filing date||Apr 4, 2006|
|Priority date||Oct 18, 1920|
|Publication number||257350, 29257350, US D612879 S1, US D612879S1, US-S1-D612879, USD612879 S1, USD612879S1|
|Original Assignee||Tokyo Electron Limited|
|Export Citation||BiBTeX, EndNote, RefMan|
|Classifications (1) |
|External Links: USPTO, USPTO Assignment, Espacenet|
Semiconductor wafer inspection apparatus
US D612879 S1
The ornamental design for a semiconductor wafer inspection apparatus, as shown and described.
FIG. 1 is a front elevational view of a semiconductor wafer inspection apparatus, showing my new design;
FIG. 2 is a bottom view thereof;
FIG. 3 is a right side elevational view thereof;
FIG. 4 is a left side elevational view thereof;
FIG. 5 is a top view thereof;
FIG. 6 is a rear elevational view thereof; and,
FIG. 7 is a perspective view thereof.
The broken line showing in each of the figures is for illustrative purposes only and forms no part of the claimed design.