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Publication numberUSD651991 S1
Publication typeGrant
Application numberUS 29/379,460
Publication dateJan 10, 2012
Filing dateNov 19, 2010
Priority dateAug 17, 2010
Also published asCA138030S
Publication number29379460, 379460, US D651991 S1, US D651991S1, US-S1-D651991, USD651991 S1, USD651991S1
InventorsTaro Nishiguchi, Makoto Sasaki, Shin Harada, Shinsuke Fujiwara, Yasuo Namikawa
Original AssigneeSumitomo Electric Industries, Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor substrate
US D651991 S1
Abstract  available in
Images(6)
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Claims(1)
  1. The ornamental design for a semiconductor substrate, as shown and described.
Description

FIG. 1 is a front, right, and top perspective view of a semiconductor substrate showing our new design;

FIG. 2 is a front view thereof, a rear view being a mirror image thereof;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a right-side view thereof, a left side view being a mirror image thereof;

FIG. 6 is a partially enlarged view at 6 shown in FIG. 2 thereof;

FIG. 7 is a partially enlarged view at 7 shown in FIG. 2 thereof;

FIG. 8 is an enlarged cross sectional view at 8-8 shown in FIG. 3 thereof; and,

FIG. 9 is a partially enlarged sectional view at 9 shown in FIG. 8 thereof.

The broken line showing of the semiconductor substrate is for the purpose of illustrating environmental structure and forms no part of the claimed design.

Non-Patent Citations
Reference
1U.S. Appl. No. 29/379,471, filed Nov. 19, 2010, Taro Nishiguchi et al.
2U.S. Appl. No. 29/379,485, filed Nov. 19, 2010, Taro Nishiguchi et al.
3U.S. Appl. No. 29/379,488, filed Nov. 19, 2010, Taro Nishiguchi et al.
4U.S. Notice of Allowance dated Aug. 3, 2011, issued in U.S. Appl. No. 29/379,485.
5U.S. Notice of Allowance dated Aug. 30, 2011, issued in U.S. Appl. No. 29/379,471.
6U.S. Notice of Allowance dated Aug. 30, 2011, issued in U.S. Appl. No. 29/379,485.
7U.S. Notice of Allowance dated Jul. 18, 2011, issued in U.S. Appl. No. 29/379,471.
8U.S. Office Action dated Jul. 22, 2011, issued in U.S. Appl. No. 29/379,488.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
USD760180 *Feb 21, 2014Jun 28, 2016Hzo, Inc.Hexcell channel arrangement for use in a boat for a deposition apparatus
USD769832 *Jul 24, 2013Oct 25, 2016Sony CorporationSemiconductor device
USD784937Apr 24, 2015Apr 25, 2017Tokyo Electron LimitedDummy wafer
USD785576Apr 24, 2015May 2, 2017Tokyo Electron LimitedDummy wafer
Classifications
U.S. ClassificationD13/182