|Publication number||USH1543 H|
|Application number||US 08/015,500|
|Publication date||Jun 4, 1996|
|Filing date||Feb 1, 1993|
|Priority date||Feb 1, 1993|
|Publication number||015500, 08015500, US H1543 H, US H1543H, US-H-H1543, USH1543 H, USH1543H|
|Inventors||William Wilber, Ahmad Safari, Milind Bedekar|
|Original Assignee||The United States Of America As Represented By The Secretary Of The Army|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Referenced by (1), Classifications (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention described herein may be manufactured, used and licensed by or for the Government for governmental purposes without the payment to us of any royalty thereon.
The invention relates in general to a thin film deposition of ferroelectric materials and in particular to a ferroelectric/silicide/silicon multilayer and to a method of making the multilayer.
For the successful development of a ferroelectric thin film, one must be able to epitaxially grow the ferroelectric on some type of substrate. For measuring the electrical properties of a ferroelectric thin film or for the design of any device that employs a ferroelectric thin film one must be able to deposit the thin film onto a material suitable as an electrode and referred to here as the bottom electrode. A second electrode can then be deposited on top of the ferroelectric film, There has been difficulty in promoting epitaxial growth of the film while simultaneously providing a bottom electrode,
The general object of this invention is to provide a ferroelectric thin film multilayer for use in any electronic device that employs ferroelectric thin films such as sensory elements or capacitors. A more specific object of the invention is to provide a barrier layer between the ferroelectric film and a silicon substrate that will also serve as an electrode. A still further object of the invention is to provide a barrier for epitaxial growth of ferroelectric on silicon and also serve as the bottom electrode for any ferroelectric device fashioned from the thin film material.
It has now been found that the aforementioned object can be attained by using a cobalt silicide (CoSi2) or nickel silicide (NiSi2) barrier layer to promote epitaxial growth and to serve as the bottom electrode,
FIG. 1 illustrates schematically how one would form the Co- or Ni- silicide/ferroelectric multilayer structure,
Beginning with a single crystal silicon substrate, a Co or Ni layer is deposited by sputtering, evaporation, laser ablation, or any other suitable means. The substrate is then annealed in an inert atmosphere at a temperature of about 750° C. that is sufficient to form a layer of CoSi2 or NiSi2 on top of the silicon. The cobalt silicide is cubic with a lattice parameter of 5.37A. Nickel silicide is cubic with a lattice parameter of 5.4A. Once the silicide has formed, one may deposit the ferroelectric layer by sputtering, laser ablation, molecular beam epitaxy or any other appropriate means. One ferroelectric material that is particularly appropriate is bismuth titanate (Bi4 Ti3 O12) because the lattice parameters are 5.41A (a axis) and 5.45A (b axis). One advantage of the deposition method shown in FIG. 1 is that the formation of the silicide layer during the anneal also acts to eliminate surface impurities such as oxides.
In the aforedescribed method, one may form the silicide layer by methods other than that shown in FIG. 1. As an example, one may deposit the silicide in one step by using molecular beam epitaxy to deposit CoSi2 or NiSi2 directly onto the silicon. This method does not have the advantage of eliminating surface impurities.
In the aforedescribed method, the silicide barrier layer can be formed in the same chamber used to deposit the ferroelectric film. This takes advantage of the fact that when the silicide grows on the silicon; the surface becomes free of many contaminants, particularly oxides. One is then able to deposit a ferroelectric onto a contaminant free surface.
In the ferroelectric/silicide/silicon multilayer of the invention, the silicon substrate is about 250 to 500 microns in thickness, the silicide layer is about 0.02 to 0.2 micron in thickness, and the ferroelectric layer is about 0.1 to 1 micron in thickness.
We wish it to be understood that we do not desire to be limited to the exact details of construction as described for obvious modifications will occur to a person skilled in the art.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5053917 *||Aug 30, 1990||Oct 1, 1991||Nec Corporation||Thin film capacitor and manufacturing method thereof|
|US5070385 *||Oct 20, 1989||Dec 3, 1991||Radiant Technologies||Ferroelectric non-volatile variable resistive element|
|US5099305 *||May 30, 1991||Mar 24, 1992||Seiko Epson Corporation||Platinum capacitor mos memory having lattice matched pzt|
|US5122923 *||Aug 30, 1990||Jun 16, 1992||Nec Corporation||Thin-film capacitors and process for manufacturing the same|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6251777||Mar 5, 1999||Jun 26, 2001||Taiwan Semiconductor Manufacturing Company||Thermal annealing method for forming metal silicide layer|
|U.S. Classification||428/446, 428/701, 428/697, 428/702|