|Publication number||USH170 H|
|Application number||US 06/818,512|
|Publication date||Dec 2, 1986|
|Filing date||Jan 13, 1986|
|Priority date||Jan 13, 1986|
|Publication number||06818512, 818512, US H170 H, US H170H, US-H-H170, USH170 H, USH170H|
|Inventors||Steven G. Binari|
|Original Assignee||United States Of America|
|Export Citation||BiBTeX, EndNote, RefMan|
|Non-Patent Citations (2), Referenced by (5), Classifications (6), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention is directed to transferred electron oscillators (TEOs), and more particularly to methods for fabricating InP TEOs.
Indium phosphide has excellent material properties for the operation of TEO devices in the millimeter-wave region of the radio spectrum. As a result of these material properties, high efficiency oscillators and low-noise broadband amplifiers have been developed. The devices used for the oscillator and amplifier development have been fabricated on n+ substrates, and accordingly, integration within a monolithic format is not easily achieved. For further application in millimeter-wave monolithic circuits, this work has focused on the development of a planar transferredelectron device formed on a semi-insulating substrate.
Planar InP TEOs have been constructed whose design includes a localized high resistivity region near the cathode contact. The high resistivity region, referred to as a notch, partially extends into the active layer and is formed by selective boron implanatation damage. This design creates a localized high electric field region, which produces a laterally uniform well-defined space-charge nucleation site. The notched devices demonstrate significantly superior microwave performance compared to devices without a notch. At x-band, notched TEO devices operate with direct current (DC) to radio frequency (RF) conversion efficiencies of up to 4.5 percent, while the TEO devices without a notch operate with an efficiency of less than 1 percent.
However for highest efficiency, the region of selective ion implantation must be aligned between the TEO device cathode and anode contacts, as close as possible to the cathode contact. As the device dimensions are decreased to meet the need of higher frequency operation, a different method of fabrication must be employed to accurately position the notch next to the cathode contact.
Accordingly, one object of the invention is to fabricate a high-efficiency planar InP TEO device.
Another object of the invention is to fabricate a high-efficiency planar InP TEO device for operation at extremely high frequencies.
Yet another object of the invention is to fabricate a high-efficiency planar InP TEO whcih includes an aligned high resistivity notch region in the device substrate between the device cathode and anode contacts.
Still another object of the invention is to fabricate a high efficiency planar InP TEO device which includes the high resistivity notch region in the device substrate aligned immediately adjacent to the cathode contact.
A further object of the invention is to fabricate a high efficiency planar InP TEO device which includes automatically aligning the high resistivity notch region in the device substate adjacent to the cathode contact.
These and other objects of the invention are achieved by a method of fabrication which includes applying a masking layer with voids in it to define cathode and anode region metallization patterns, slant evaporating a metallic film onto the masking layer to form an uncoated region adjacent to the cathode region, and ion implanting the uncoated area to form a high resistivity notch region in the substrate immediately adjacent to the cathode region. Removal of the masking layer with its metallic film coating followed by alloying then forms a planar InP TEO device structure with an automatically aligned high resistivity notch region.
Other objects, features and advantages of the invention will be apparent to those skilled in the art in the description of the preferred embodiment of the invention as described below and also recited in the appended claims.
FIG. 1 shows a self-aligned notch InP TEO device as produced by the fabrication process according to the invention.
FIG. 2 shows the doped semiconductor substrate selected for the fabrication process according to the invention.
FIG. 3 shows the slant evaporation phase of the fabrication process according to the invention.
FIG. 4 shows the oxygen implanatation phase of the fabrication process according to the invention.
FIG. 5 shows the completed self-aligned TEO structure after the alloying phase of the fabrication process according to the invention.
Referring to the drawings, wherein like reference characters designate like or corresponding parts throughout the views, FIG. 1 shows a cross-sectional side view of the desired device structure for the self-aligned InP TEO. An indium phosphide substrate 10 has an n-doped epitaxial surface layer 12. The surface layer 12 includes an n+ -doped anode region 14 which partially penetrates the surface layer 12. The anode region 14 has an ohmic anode contact 16 on its surface. An area of said surface layer 12 has an ohmic cathode contact 18 on its surface. Between the cathode contact 18 and the anode contact 16, a high-resistivity impurity-containing notch region 20 partially penetrates the surface layer 12 immediately adjacent to the cathode contact 18.
The fabrication process of the invention is illustrated in FIGS. 2 through 5. As shown in FIG. 2, a semi-insulating InP substate 22 is selected having an epitaxially grown n-type InP surface layer 24 with at least one n+ -doped anode region 26 imbedded in the surface layer 24. By way of example, a suitable substrate 22 may have an epitaxial surface layer 24 in the range of 0.8 to 1.5 μm in thickness, but preferably in the range of 0.9 μm in thickness, with a carrier concentration in the range of 1 to 10×1016 cm-3, but preferably in the range of 6×1016 cm-3, and the n+ -doped anode region 26 may be formed in the surface layer 24 by selective ion implantation, as will be recognized by those skilled in the art.
As shown in FIG. 3, a masking layer 28, which may be, by way of example, a photoresist mask in the range of 1 μm in thickness, is applied over the surface of the surface layer 24. The masking layer 28 includes two voids through it, one void over the anode region 26, and the other void closely spaced to the anode region to define a cathode region 30. A metallization layer 32 is then evaporated onto the masking layer 28 at an angle from perpendicular to the masking layer 28, having a slant in a direction from the anode region 26 toward the cathode region 30. By way of example, the metallization layer 32 may comprise a laminate of gold over gold germanium layers each in the range of 1000 Å in thickness, evaporated onto the masking layer 28 at an angle in the range of 10 to 45 degrees, but preferably in the range of 22 degrees. By evaporating the metallization layer 32 at an angle, the metallization layer 32 acquires a narrow void region 34 between the cathode region 30 and masking layer 28 due to the shadow effect of the edge of the masking layer 28.
As shown in FIG. 4, the surface of the metallization layer 32 is then subjected to ion implantation. Ions only penetrate into the substrate surface layer 24 through the metallic layer void region 34, creating a high resistivity notch region 36 penetrating the surface layer 24. By way of example, oxygen atoms may be implanted to create the high resistivity notch region 36.
As shown in FIG. 5, the masking layer 28 is then chemically removed, and the portion of the metallization layer in contact with it is stripped off. The substrate is then alloyed to change the remaining portion of the metallization layer 32 covering the cathode region 30 into an ohmic cathode contact 38, and the portion covering the anode region 26 to an ohmic contact 40. By way of example, alloying at a temperature of about 400° C. for a period of 30 seconds is sufficient, as will be apparent to those skilled in the art.
It will be understood that various changes in the details, materials and arrangement of steps and components which have been herein described and illustrated in order to explain the nature of the invention may be made by those skilled in the art.
|1||"Notched InP Planar Transferred Electron Oscillators," S. C. Binari et al., International Electron Devices Meeting, Dec. 1982.|
|2||"Self-Aligned Notched Planar InP Transferred-Electron Oscillators," S. C. Binari et al., IEEE Electron Device Letters, EDL-6, No. 1, Jan. 1985.|
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|U.S. Classification||438/523, 427/250, 331/107.00R|
|Mar 13, 1986||AS||Assignment|
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:BINARI, STEVEN G.;REEL/FRAME:004519/0643
Effective date: 19860113
Owner name: UNITED STATES OF AMERICA AS REPRESENTED BY THE SEC