US H1993 H1 Abstract A circuit calculates the exact biased resultant exponent before calculating the resultant mantissa of a division operation. The circuit includes a carry-save adder, a conditional-sum adder, a multiplexer and a comparator. The conventional carry-save adder receives the biased exponent of the dividend (e1), the one's complement of the biased exponent of the divisor (˜e2), and the bias. The conditional-sum adder receives the sum and carry resultants of the carry-save adder, outputting {er0=e1+(˜e2)+bias} and {er1=e1+(˜e2)+bias+1}. The comparator controls the multiplexer to respectively select as the resultant exponent either er0 or er1 when the fraction of the dividend is less than or greater than or equal to the fraction of the divisor. A circuit for determining the resultant exponent of a squareroot operation includes a conditional-sum adder, a multiplexer and a selection logic circuit. The conditional-sum adder receives ½ of e2 and an adjusted bias. The adjusted bias is ½ of the bias (incremented if e2 is odd), causing the conditional-sum adder to output {er0=½e2+adjusted bias} and {er1=½e2+adjusted bias+1}. The selection logic controls the multiplexer to select er0, except in the case in which all three of the following conditions exist: (i) the fraction of the operand has no zeros; (ii) the squareroot operand is even; and (iii) the rounding mode is rounding to positive infinity.
Claims(17) 1. A circuit for determining a resultant exponent of a floating-point division operation of a dividend and divisor, the dividend and divisor each having a fraction and a biased exponent, the circuit comprising:
an adder circuit configured to receive the biased dividend exponent (e1), a one's complement of the biased divisor exponent (
^{˜}e2) and a bias, wherein said adder circuit generates output sums er0 and er1, wherein sum er0 is equal to e1 +(^{˜}e2)+bias, and sum er‘b is equal to er0+1; a multiplexer coupled to receive the sums er0 and er1 from said adder circuit; and
a selection logic circuit coupled to said multiplexer, and coupled to receive the dividend fraction and the divisor fraction, wherein said selection logic circuit causes said multiplexer to select the sum er0 when the dividend fraction is less than the divisor fraction without waiting for a result of a mantissa computation.
2. The circuit of claim
1 wherein said selection logic causes said multiplexer to select the sum er1 when the dividend fraction is greater than or equal to the divisor fraction.3. The circuit of claim
2 wherein said selection logic comprises a comparator coupled to receive the divisor fraction and the dividend fraction.4. The circuit of claim
1 wherein said adder circuit comprises a carry-save adder and a conditional-sum adder.5. The circuit of claim
4 wherein said carry-save adder is coupled to receive the biased dividend exponent (e1), the one's complement of the biased divisor exponent (^{˜}e2) and the bias.6. The circuit of claim
1 further comprising a underflow detector and an overflow detector, said underflow and overflow detectors coupled to receive the sum selected by said multiplexer.7. The circuit of claim
1 further comprising a first and second underflow detectors and a first and second overflow detectors, said first underflow and overflow detectors coupled to receive the sum er0 from said adder circuit, and said second underflow and overflow detectors coupled to receive the sum er1 from said adder circuit.8. A circuit for determining a resultant exponent of a floating-point squareroot operation of an operand having a fraction and a biased exponent (e2), the circuit comprising:
an adder circuit configured to receive e2 and a constant B, wherein said constant B is a bias when e2is even and the bias+1 when e2 is odd wherein said adder is configured output sums er0 and er1, wherein er0 is equal to ½(e2+B), and er1 is equal to er0+1;
a multiplexer coupled to receive the sums er0 and er1 from said adder circuit; and
a selection logic circuit coupled to said multiplexer, wherein said selection logic circuit is configured to cause said multiplexer to select the sum er1 when the fraction of the operand has no zeros, e2 is even, and said circuit is configured in a round to positive infinity mode.
9. The circuit of claim
8 wherein said selection logic circuit is further configured to select the sum er1 only when the fraction of the operand has no zeros, e2 is even, and said circuit is configured in a round to positive infinity mode.10. The circuit of claim
8 wherein said selection logic circuit is further configured to select the sum er0 when any of the following conditions are true: the operand has a zero, e2 is odd, or said circuit is not configured in the round to positive infinity mode.11. The circuit of claim
8 wherein said adder circuit comprises a conditional-sum adder.12. A circuit for determining a resultant exponent of a floating-point division operation during a division mode, a floating-point squareroot operation during a squareroot mode and a floating-point multiplication operation during a multiplication mode, each operand of the division, squareroot and multiplication operations having a normalized mantissa and a biased exponent, each mantissa having a fraction, the circuit comprising:
a first multiplexer configured to receive the biased exponent (e1) of the first operand and a zero, wherein said first multiplexer is selectably configured to provide as an output operand at an output port of said first multiplexer either zero during the squareroot mode or e1 during the division and multiplication modes;
a second multiplexer configured to receive the biased exponent (e2) of the second operand, ½e2, and a one's complement of e2 (˜e2), wherein said second multiplexer is selectably configured to provide as an output operand at an output port of said second multiplexer either e2 during the multiplication mode, ½e2 during the squareroot mode or ˜e2 during the division mode;
a third multiplexer configured to receive constants B
1-B4, B1 being equal to a bias, B2 being equal to the ½(bias), B3 being equal to ½(bias+1), and B4 being equal to a one's complement of the bias, wherein said third multiplexer is selectably configured to provide as an output operand at an output port of said third multiplexer either B1 during the division mode, B2 during the squareroot mode when e2 is even, B3 during the squareroot mode when e2 is odd, and B4 during the multiplication mode; an adder circuit having first, second and third input ports respectively coupled to said output ports of said first, second and third multiplexers, wherein said adder circuit is configured output sums er0 and er1, wherein er0 is equal to a sum of the output operands of said first, second and third multiplexers, and wherein er1 is equal to er0+1;
a fourth multiplexer coupled to receive er0 and er1 from said adder circuit; and
a selection logic circuit coupled to said fourth multiplexer, wherein said selection logic circuit is configured to cause said fourth multiplexer to select the sum er1 when:
the first operand's fraction is greater than or equal to the second operand's fraction when said circuit is in the division mode,
the second operand's fraction has no zeros, e2 is even, and said circuit is configured in the squareroot mode with a round to positive infinity rounding mode, and
a product of the mantissas of the first and second operands is greater than or equal to two when the circuit is in the multiplication mode.
13. The circuit of claim
12 wherein said adder circuit comprises a carry-save adder and a conditional-sum adder.14. The circuit of claim
12 wherein said selection logic circuit comprises a comparator configured to receive the fractions of the operands during the division mode.15. The circuit of claim
12 wherein said selection logic circuit further comprises a decoder configured to receive the fraction of the second operand, a first signal, and a second signal, said first signal having a logic one value when the circuit is in the round to positive infinity rounding mode, and said second signal having a logic one value when e2 is even.16. The circuit of claim
12 further comprising first and second underflow detectors and first and second underflow detectors, said first underflow and overflow detectors coupled to receive er0 from said adder circuit, and said second underflow and overflow detectors coupled to receive er1 from said adder circuit.17. The circuit of claim
12 wherein the bias is equal to 127 when the circuit is operating in a single precision mode and 1023 when the circuit is operating in a double precision mode.Description The present invention relates to processors and, more particularly, to circuitry for performing floating-point division and squareroot operations. Many currently available processors are configured to perform floating-point arithmetic such as, for example, division and squareroot, in compliance with the IEEE Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Std 754-1985). which is incorporated herein by reference. In these processors, the exponent of the result of the operation is generally calculated after the mantissa computation is completed. Thus, the calculation of the resulting exponent is in the critical path of the division and squareroot operations. Moreover, the mantissa computation can require twenty or more processor clock cycles to complete when using double precision. Thus, calculation of the resultant exponent has a relatively long latency. As is well known, the resultant exponent can then be checked for overflow and underflow exceptions, which are defined in the aforementioned IEEE standard. The relatively long latency of the resulting exponent calculation can become problematic in the so-called superscalar type of processor. In particular, because superscalar processors may concurrently execute two or more instructions, an instruction may complete after a later-occurring instruction, which can result in an error. For example, an error may occur if the later-occurring instruction overwrites a register before a prior floating-point division instruction completes and an overflow or underflow exception occurs for a prior floating-point division operation. The error occurs because when an exception occurs during an instruction (i.e., the trapping instruction), the processor is required to abort all subsequent instructions and request a trap. After the trap-handler completes execution of the trapping instruction, the processor is restarted at the instruction immediately after the trapping instruction. Of course, the completion of a subsequent instruction that overwrites a register before the exception is handled by the trap-handler can cause an error in the program execution. Because the resultant exponent is not calculated until late in the instruction execution, a conventional solution to this problem is to make a prediction (before the next subsequent instruction completes) of whether an overflow or underflow exception will occur. In this conventional scheme, a pessimistic prediction is performed to ensure that no overflow or underflow exceptions will be missed by the trap-handler. Of course, pessimistic prediction will result in unnecessary traps, which decreases the performance of the processor. Thus, there is a need for a processor capable of early and exact calculation of the resultant exponent, which both increases performance and allows exact prediction of overflow and underflow. In accordance with the present invention, a floating-point division circuit is provided that calculates the exact biased resultant exponent before calculating the resultant mantissa. In one embodiment, the circuit includes a carry-save adder, a conditional-sum adder, a multiplexer and a comparator. The conventional carry-save adder is coupled to receive the biased exponent of the dividend (e1), the one's complement of the biased exponent of the divisor (˜e2), and the bias (as defined in the aforementioned the ANSI/IEEE Standard for the precision format being used). The ANSI/IEEE Standard specifies that the mantissas of the dividend and operand can be in normalized form. The conditional-sum adder is coupled to receive the sum and carry resultants of the carry-save adder and operates to output the sums {er0=e1+(˜e2)+bias} and {er1=e1+(˜e2)+bias+1}. The sum er0 is the resultant biased exponent of the division operation when the resultant mantissa is in a normalized form after calculation. Similarly, the sum er1 is the resultant biased exponent of the division operation when the resultant mantissa is not in a normalized form. The comparator provides an output signal that controls the multiplexer to select the sum er1 when the fraction of the dividend is greater than or equal to the fraction of the normalized divisor. Conversely, when the fraction of the normalized dividend is less than the fraction of the normalized divisor, the comparator causes the multiplexer to select the sum er0. Because the operation of the carry-save adder, conditional-sum adder and the comparator is relatively fast, the exact resultant exponent is available for underflow and overflow detection before the next instruction completes, thereby eliminating the need for pessimistic prediction. In another embodiment of the invention adapted for determining the resultant exponent of a floating-point squareroot operation, the circuit includes a conditional-sum adder, a multiplexer and a selection logic circuit. The conditional-sum adder is coupled to receive the biased exponent (e2) of the squareroot operand, divided by two (i.e., right-shifted by one bit) and an adjusted bias. The adjusted bias is the exponent bias divided by two, which is incremented if the exponent e2 is odd (i.e., having a least significant bit equal to one). Thus, the conditional-sum adder outputs the sum {er0=½e2+adjusted bias} and the sum {er1=½e2+adjusted bias+1}. The resultant mantissa will end up in normalized form after calculation, except in the case in which all three of the following conditions exist: (i) the fraction of the operand has no zeros; (ii) the e2 is even; and (iii) the rounding mode is rounding to positive infinity (as defined in the aforementioned IEEE standard). The selection logic monitors these three conditions and causes the multiplexer to select er0 to output as the biased resultant exponent in all cases except when all three of the above-conditions occur. When all three of these conditions occur, the selection logic causes the multiplexer to select er1 to output as the biased resultant exponent. This embodiment determines the exact biased resultant exponent before the mantissa calculation is completed. Thus, unlike conventional squareroot circuits, the resultant exponent calculation is taken out of the critical path, thereby improving performance. In yet another embodiment, the circuit is adapted to calculate the biased resultant exponent of floating-point division, squareroot and multiplication operations. This embodiment includes a bias selection circuit, a first multiplexer, a second multiplexer, a carry-save adder, a conditional-sum adder, a selection logic circuit and an output multiplexer. The first multiplexer selects either e1 for multiplication and division operations or zero for squareroot operations. The second multiplexer selects e2 for multiplication operations, (˜e2) for division operations or ½e2 for squareroot operations. The bias selection circuit selects the appropriate bias for the precision format (e.g., single or double precision) for division operations or the adjusted bias (for single or double precision) for squareroot operations. The carry-save adder receives the selected output signals of the first and second multiplexers and the bias selection circuit. The conditional-sum adder receives the carry and sum output signals of the carry-save adder and outputs the sums er0 and er1. The selection logic circuit then causes the output multiplexer to select either er0 or er1 as described above for the floating-point division and squareroot embodiments. For floating-point multiplication operations, the selection logic circuit detects whether the mantissa multiplication resultant is normalized or not normalized. If the mantissa is normalized, the selection logic circuit causes the output multiplexer to select er0 and, conversely, if the mantissa is not normalized, the selection logic circuit causes the output multiplexer to select er1. In a further refinement of this embodiment, two conventional overflow and two underfiow detectors may be coupled to respectively receive the er0 and er1 signals from the conditional-sum adder so that the overflow and underflow of er0 and er1 may be determined concurrently with calculation of the multiplication mantissa resultant. The selection logic circuit is also implemented to select the output signals of the appropriate overflow and underflow detectors. This embodiment allows the use of same resultant exponent circuitry (which takes the resultant exponent calculation out of the critical path) for floating-point multiplication, division and squareroot operations. In addition, for the case of multiplication and division operations, the biased resultant exponent is calculated significantly faster, thereby eliminating the need for pessimistic prediction of the overflow or underflow of the resultant exponent. The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: FIG. 1 is a block diagram of a computer system having a floating-point processor with circuitry for calculating resultant exponents according to the present invention; FIG. 2 is a block diagram of a circuit for determining the resultant exponent of floating-point division operations, in accordance with one embodiment of the present invention; FIG. 3 is a block diagram of a circuit for determining the resultant exponent of floating-point squareroot operations, in accordance with one embodiment of the present invention; FIG. 4 is a logic diagram of a selection logic circuit, in accordance with one embodiment of the present invention; FIG. 5 is a block diagram of a block diagram of a circuit for determining the resultant exponent of floating-point multiplication, division and squareroot operations, in accordance with one embodiment of the present invention. FIG. 1 is a block diagram of an electronic system This embodiment of the electronic system FIG. 2 is a block diagram of a circuit
where operand1 is the dividend and mantissa1 and e1 respectively are the mantissa and the biased exponent of the dividend, and where operand2 is the divisor and mantissa2 and e2 respectively are the mantissa and biased exponent of the divisor. The circuit In this embodiment, the circuit The carry-save adder
where er0 is the biased resultant exponent of the floating-point division operation when the mantissa calculation results in a non-normalized result, and er1 is the biased resultant exponent of the floating-point division operation when the mantissa calculation results in a non-normalized result. Equations 2 and 3 apply in this embodiment because the mantissas of both the dividend and the divisor are greater than or equal to one and less than two (i.e., in binary form, the mantissa of each operand has an implicit or hidden “1” to the left of the decimal point). Accordingly, the mantissa of the resultant of the division operation must be greater than ½ and less than two. Further, when the fraction (i.e., the portion of the mantissa to the right of the decimal point) of the dividend is less than the fraction of the divisor, the mantissa of the resultant must be greater than ½ and less than one. Therefore, in this case the resultant mantissa is non-normalized (i.e., with a zero to the left of the decimal point) and is right shifted once to be normalized. This right shift of the resultant mantissa requires that the resultant exponent by decreased by one. Further, the biased resultant exponent is the biased exponent of the dividend minus the biased exponent of the divisor. As is well known in binary arithmetic, subtraction of a number is equivalent to the addition of the number's two's complement. However, because the resultant exponent in this case must be decremented by one, the one's complement of the divisor is used. Thus, equation 2 determines the exact biased resultant exponent when the fraction of the dividend is less than the fraction of the divisor. Conversely, when the fraction of the dividend is greater than or equal to the fraction of the divisor, the mantissa of the resultant must be greater than or equal to one and less than two. Therefore, the resultant mantissa (in binary form) has a “1” to the left of the decimal point as shown in the following equation:
where each “X” represents a either a “1” or a “0” (i.e., a “don't care” bit). Thus, in this case, the resultant mantissa is already normalized. Consequently, because only the one's complement of the divisor was added, the resultant exponent must be incremented by one so that, in effect, the two's complement of the divisor was added. Accordingly, equation The comparator Further, because the exact biased resultant exponent is available after about one processor clock cycle, a conventional underflow detector In a further refinement of this embodiment, the bias received by the carry-save adder FIG. 3 a block diagram of a circuit
where SQRT{ } represents the squareroot of the number within the brackets. The circuit In this embodiment, the circuit
where the adjusted bias is ½ of the normal bias (for the precision format being used), which is incremented if e2 is odd. The adjusted bias is added for the following reason. In binary arithmetic, dividing an exponent by two can be easily implemented by shifting the exponent one place to the right of the decimal point and truncating the least significant bit. Thus, when e2 is even, no accuracy is lost in dividing e2 by two and the adjusted bias remains ½ of the bias specified in the ANSI/IEEE Standard for the precision format being used. However, if e2 is odd, the right shift operation loses the least significant bit, resulting in a loss of accuracy in the resultant exponent. Therefore, e2 is reduced by one while increasing the mantissa by a factor of two. Of course, this adjusted operand is equivalent to the original normalized operand. Then, in dividing the exponent by two, the bias is reduced by a further ½, as shown in the following equations:
where SQRT{ } represents the squareroot of the operand within the brackets and e2 is odd. In order to properly bias the resultant exponent, an additional (½bias+½) needs to be added to the exponent so that the resultant exponent is equivalent to (½e2+bias). Thus, when e2 is odd, the adjusted bias is (½bias+½) or ½(bias+1). The adjusted biases for even and odd e2 are summarized below in Table 1.
It can be shown that the squareroot of a normalized operand (i.e., greater than or equal to one but less than two) is between 1 and the square root of two, inclusive. Thus, the resultant mantissa of the squareroot of a normalized operand mantissa is always normalized. In addition, it can be shown that the squareroot of an operand greater than or equal to two and less than four (i.e., the “even e2” mantissa) is greater than or equal to the square root of two and less than two. Consequently, the resultant mantissa of the squareroot of the adjusted mantissa in the “even e2” case is also always normalized. Because the resultant mantissa is always normalized, there can be no overflow or underflow. Thus, the resultant exponent er will always be equivalent to er0 as provided by the conditional-sum adder The ANSI/IEEE Standard includes a rounding mode called round to positive infinity (rp). In this rounding mode, the resultant mantissa calculation may not always result in a normalized number. In particular, the resultant mantissa after the squareroot operation may not be in normalized form under the following conditions: (i) the operand mantissa has no zeros; (ii) e2 is even; and (iii) the rounding mode is rounding to positive infinity (as defined in the aforementioned ANSI/IEEE Standard). As can be shown, when the operand mantissa has no zeros, the squareroot of this mantissa will also have no zeros. As defined in the ANSI/IEEE Standard, in the rp rounding mode, if the resultant mantissa has any “1”s to the right of the least significant bit for the precision format (i.e., bit In the circuit FIG. 4 is a logic diagram showing an embodiment of the selection logic circuit FIG. 5 is a block diagram of a circuit The first multiplexer The second multiplexer The bias selection circuit The carry-save adder However, for multiplication operations, the carry-save adder The conditional-sum adder
where (˜bias) is the one's complement of the bias for the precision format (single or double precision) being used. In this embodiment, in addition to being received by the multiplexer The selection logic circuit Of course, in other embodiments, the selection control circuit In a further refinement of this embodiment, two conventional overflow and two underflow detectors may be coupled to respectively receive the er0 and er1 signals from the conditional-sum adder so that the overflow and underflow of er0 and er1 may be determined concurrently with calculation of the multiplication mantissa resultant. The selection logic circuit is also implemented to select the output signals of the appropriate overflow and underflow detectors. This embodiment allows the use of same resultant exponent circuitry (which takes the resultant exponent calculation out of the critical path) for floating-point multiplication, division and squareroot operations. In addition, for the case of multiplication and division operations, the resultant exponent is calculated significantly faster, thereby eliminating the need for pessimistic prediction of the overflow or underflow of the resultant exponent. The methodology of the embodiments described above is further described in co-pending and co-filed patent application Ser. No. 08/882,250 by the present inventor, which is incorporated herein by reference. The embodiments of the floating-point division and squareroot circuitry of the present invention described above are illustrative of the principles of this invention and are not intended to limit the invention to the particular embodiments described. For example, while the embodiments described are configured for use in a thirty-two-bit word length system, other embodiments can be adapted by those skilled in the art of floating-point processors for use in systems with different word lengths. In another example, those skilled in the art can combine the division and squareroot circuits without the multiplication circuit. Accordingly, while the preferred embodiment of the invention has been illustrated and described, it will be appreciated that in light of the present disclosure various changes can be made to the described embodiments without departing from the spirit and scope of the invention. Patent Citations
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