US H368 H
A method of improving field-effect transistors, and the product thereof, wherein the resistivity of the upper layer of the source-gate channel region of a GaAs field-effect transistor (FET) may be selectively raised is disclosed. Impurity ions are implanted in the source-gate channel region followed by a much shallower implantation of boron in the same region. The boron ion concentration should exceed the N+ impurity ion concentration by a factor of 2 or more.
1. A cooled wall having an internal surface defining a portion of a coolant compartment and an external surface adapted to have a hot gas flowing thereover in a downstream direction tangent to said external surface, a coolant passage through said wall having an inlet communicating with said compartment for receiving coolant fluid therefrom and an outlet at said external surface, said passage including, in series flow relation, a metering portion comprising a flow area of constant cross section for metering the flow of coolant fluid through said passage, a diffusing portion having an increasing cross-sectional flow area in the direction toward said outlet, and a nozzle portion terminating at said outlet, said nozzle portion including first wall surface means defining a flow path oriented to direct a flow of fluid therefrom in the generally downstream direction at a shallow angle relative to said external surface, wherein said flow path simultaneously diverges to said outlet in a longitudinal direction perpendicular to the downstream direction, and converges toward and substantially to said outlet in a direction perpendicular to the longitudinal direction, wherein said outlet is elongated in the longitudinal direction.
2. The cooled wall according to claim 1 wherein said first wall surface means comprises a downstream surface which faces generally upstream and intersects said external surface at a shallow angle defining a longitudinally extending downstream edge of said outlet.
3. The cooled wall according to claim 2 wherein said metering portion has a straight central axis passing through the geometric center of its cross-sectional area and extending through the length of said diffusing portion, said first wall surface means of said nozzle portion including a surface located to completely block a line of sight of said metering portion along said central axis.
4. The cooled wall according to claim 1 wherein said wall is the external wall of a hollow airfoil, and the longitudinal direction is the spanwise direction of said airfoil, said wall including a plurality of said passages therethrough spaced apart in a longitudinally extending row.
5. The cooled airfoil wall according to claim 4 wherein said diffusion portion includes second wall surface means defining a flowpath which diverges along its entire length in both the longitudinal direction and in a direction perpendicular to the longitudinal direction.
6. The cooled airfoil wall according to claim 5 wherein said first and second wall surface means each comprise a downstream surface which faces generally upstream, said downstream surfaces being coextensive, extending from said metering portion to said passage outlet and intersecting said external surface of said airfoil at a shallow angle.
7. The cooled airfoil wall according to claim 6 wherein said coextensive downstream surfaces are flat surfaces and define a longitudinally extending downstream edge of said outlet at the intersection of said external surface.
8. The cooled airfoil wall according to claim 7 wherein the cross-sectional area of said passage perpendicular to the direction of flow therethrough is generally rectangular in shape along the length of said diffusing and nozzle portions.
9. The cooled airfoil wall according to claim 4 wherein said first wall surface means comprises a longitudinally extending downstream surface which faces generally upstream and a longitudinally extending upstream surface which is spaced from and faces said downstream surface and converges toward said downstream surface to direct the coolant fluid toward said downstream surface.
10. The cooled airfoil wall according to claim 9 wherein said downstream surface intersects said external surface at an angle no greater than about 40° and defines a longitudinally extending downstream edge of said passage outlet at the intersection of said external surface.
11. The cooled airfoil wall according to claim 10 wherein said metering portion intersects said internal surface of said airfoil wall and includes a central axis passing through the geometric center of said constant cross sectional flow area, and wherein said diffusing portion includes a longitudinally extending first surface facing generally downstream and parallel to said central axis for substantially the length of said diffusing portion and a longitudinally extending second surface facing said first surface and diverging therefrom toward said outlet for the full length of said diffusing portion.
12. The cooled airfoil wall according to claim 11 wherein said diffusing portion second surface is coplanar with said nozzle portion downstream surface.
13. The cooled wall according to claim 1 wherein said first wall surface means comprises a longitudinally extending downstream surface which faces generally upstream and a longitudinally extending upstream surface which is spaced from and faces said downstream surface and converges toward said downstream surface to direct the coolant fluid toward said downstream surface.
14. The cooled wall according to claim 13 wherein said metering portion has a straight central axis passing through the geometric center of its cross-sectional area and extending through the length of said diffusing portion, said upstream surface located to at least partially block a line of sight of said metering portion along said central axis.
This invention relates to an improved field-effect transistor (FET) and especially to improvement of FET's by tailoring the source-gate channel resistivity to be high in the upper layer and lower in the lower layer.
Transconductance, gate capacitance, source parasitics, and source-gate channel resistance are the factors universally known to affect the performance of field-effect transistors. Previous work in the field has done much to improve transconductance by improving materials' quality and materials' interfaces. Gate capacitance has been reduced by using submicrometer resolution lithography. Source parasitics have been greatly reduced by better metallization for ohmic contacts by "via" technology and by monolithic, Class B, push-pull circuit techniques. Only source-gate channel resistance has evaded a solution enabling it to be reduced without adversely affecting gate leakage characteristics.
Accordingly, it is an object of this invention to reduce the source-gate channel resistance in an FET without adversely affecting the gate leakage characteristic.
Another object is to raise the resistivity of a shallow layer of the source-gate channel in an FET, which layer is in contact with the Schottky-barrier portion of the gate, without increasing the resistivity of the remainder of the source-gate channel.
The above and other objects of the invention are accomplished in a GaAs FET by selectively bombarding the N+ doped source-gate channel region with boron ions to raise the resistivity of a shallow upper layer of the channel which is in contact with the Schottky-barrier film of the gate without increasing the resistivity of the underlying channel region. The technique makes use of the virtual non-existence of ionicity in the boron-arsenide bond to induce arsenic vacancies within the crystal which may, in part, be filled with column IV acceptors (e.g., silicon) with the result that deep-level compensating centers are formed (probably by silicon-silicon complexes) thereby transforming the material so treated into semi-insulating material.
FIG. 1 is a schematic illustration of a prior-art FET made by an epitaxial growth technique.
FIG. 2. is a schematic illustration of a prior-art FET made by an ion implantation technique.
FIG. 3 is a schematic illustration of an embodiment of the present invention.
FIGS. 1 and 2 illustrate the construction of typical priorart FET's. The FET of FIG. 1 is produced by the growth of epitaxial layers 12 and 14 on a semi-insulating GaAs substrate 10. Layer 14 has a higher concentration of donor impurity ions (approximatel 1×1017 /cm3) than lower layer 12 and therefore has higher conductivity. The active layer 14 in FIG. 2 is produced by implantation of donor ions. The device also includes a source 16, a drain 18 and a gate 20. In both cases, the active channel, which may, for example, be about 0.5 microns deep, is uniformly doped in the horizontal direction (i.e., along the direction of charge-carrier movement).
Referring now to FIG. 3, the source-gate channel region 28, including a top portion 26 and a bottom portion 26', between source 16 and gate 20 (Schottky barrier gate) should be of much lower resistivity than a region 24 lying beneath the gate 20 and between the gate 20 and the drain 18. If the source-gate channel region 28 is heavily doped, however, the leakage of the Schottky barrier gate 20 is excessive. Techniques to create a vertical gradient of resistivity in this region have thus far been unsuccessful since there has been no ion implantation technology capable of reproducibly creating such a gradient. The ideal characteristic is one in which the electrically active impurity concentration at the top portion 26 of the source-gate channel region 28 is less than or equal to that of the region 24 directly beneath the gate 20, while the electrically active impurity concentration in the lower portion 26' of the source-gate channel region 28 is at least an order of magnitude greater than the impurity concentration in the same region 24 directly beneath the gate 20. The achievement of such an impurity gradient profile virtually eliminates the source-gate channel resistance as a significant factor adversely affecting FET performance and the gradient does not adversely affect the characteristics of the Schottky-barrier gate 20.
To achieve this optimum gradient profile in the source-gate channel region 28 without adversely changing the impurity profile elsewhere requires a new approach based on an understanding of how impurity complexes can be used to reproducibly and reliably control the properties of semiconductors. The implantation of boron is known to render GaAs semi-insulating since it compensates, or neutralizes, other impurities which render the GaAs more conductive. Thus the effect of the boron is to render the doped GaAs more insulative. Only recently has it been found that the boron implant dose need not be excessive to the extent of rendering the semiconductor amorphous but, instead, need only exceed the concentration of other impurities within the GaAs. More recently, it has been shown that boron implanted in GaAs does not diffuse within the GaAs at elevated temperatures as do most other impurities.
Still referring to FIG. 3, to the optimum gradient profile in the source-gate channel region 28 of the improved ion-implanted FET shown, an impurity ion is selected (e.g., Si, or Si and S) and selectively implanted into the source-gate channel region 28. This may be done simultaneously with the N+ selective source and drain implants in regions 22 and 30, respectively. (In this context, the term "selectively" applies to the particular region selected for any ion implantation.) As shown, the region 24 is implanted only to the N state, or a concentration of about 1×1017 /cm3. However, the other regions 22, 28 and 30, as aforementioned, are implanted to the N+ state, or a concentration of about 1×1018 /cm3. These implants are then followed by a much shallower (i.e., done with a lower implantation voltage) implant (e.g., 200-500 Å) of boron into the top portion 26 of source-gate channel region 28. By so doing, As vacancies are created in the top portion 26 but not in the bottom portion 26' of the source-gate channel region 28. The concentration of the boron implant should exceed the concentration of the N+ impurity by a factor of 2 or more to ensure that some As vacancies remain in the top portion 26 after other As vacancies are filled by the acceptor (silican) ions previously implanted. The maximum concentration of boron should be below that which would cause the GaAs to become amorphous; thus, the concentration should not be more than about 5×1019 /cm3.
Activation/annealing of the implanted ions may then proceed in a conventional manner chosen by the fabricator (i.e., thermal, laser and/or electron beam). The annealing ambient must be chosen so that the boron-implanted region, i.e., top portion 26, is not etched away in the process (e.g., use flowing arsine, proximity capping or a good silicon nitride encapsulant).
Obviously, many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the invention can be practiced otherwise than as specifically described.