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Publication numberUSRE28265 E
Publication typeGrant
Publication dateDec 10, 1974
Filing dateFeb 4, 1974
Priority dateDec 29, 1969
Publication numberUS RE28265 E, US RE28265E, US-E-RE28265, USRE28265 E, USRE28265E
InventorsJohn W. Irwin
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Svc out
US RE28265 E
Abstract  available in
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Claims  available in
Description  (OCR text may contain errors)

J. w. IRWIN Re. 28, 265



INTEL-RECORD RESYNCBROHIZATIOH I}! DIGITAL-RECORDING SYSTEMS Original Filed Dec. 29, 1969 11 Sheets-Sheet 4 FROM FIG. 51 STEP 14 T 111 an STOP CYCLE RESET WRlTE 011111 CYCLE 11111115 A? 1111111511 51cm I j 1 1 i 1 1 1 /89 1 1 ALTER 111m 1 BYTE cow 1 110111111;

L/ 1 1 1 I 1 1 1 1 111111 1 1 1 l i ljj ijjiiijjjj; r

\ r 1 1 1 11mm /80 1 1 1 1 5111c BURST I 1 1 1 $191111 1 I 1 1 92 1 WRITE 1 I 1 POSTAMBLE l 1 1 1111511 1 ,(END 19 1 END 15 1 1 01111111 1 i I I 1 1 1 1 1 l t .I i 1 1 1 1 1 1 l STEP 65 Doc. 10, 1974 J. W. IRWIN DETECT INTRARECORD HESYNCHRONIZATIOH IN DIGITAL-RECORDING SYSTEMS Original Filed Dec. 29, 1969 11 Sheets-Sheet 5 FIG. 4 BEGINNING or RECORD BLOCK ER'D'R'RE" FORWARD '2 5|GNAL5 1o9 ALTER BYTE coum MARKER 5mm '2 YES YES TRANSFER 3%??? RR SEOUENCE- 1oe WAIT TWO 105x CLOCK CYCLES l REENTER READ SET SEOUENCE\ STEERING READ DATA M /m BYTAELTCEJEJNT READ RESYNC CYCLE (FIG. 5)

END OF DATA Dec. 10, 1974 J. w. mwm Re. 28, 265



INTRARECORD RESYNCHHONIZA'I'ION IN DIGITAL-RECORDING SYSTEMS Original Filed Dec. 29, 1969 11 sheets sheat 7 BLUCK 221 ,220 DETECTEOQ 222 INITIAL (m 2) 152 "A E AQ READ 259 (FIGS) RESET LE A 200 a FWD. 2


(E|r;.n* *JA} Z STEERING jA|-{M2 I OTC 33 139 WRITEI 2 CLOCK A 0 /38A 140 #0 CHL. SVC. IN m1) 3A 11s READ DATA-1255 (FIG. a)

SET svom [194 as 1 W svc. m cumom 7 0 /5T svc. our END OF PREAMBLE 6 m ,155 156 15 V WRITE I 144 246 BYTE DETECT Ego mom 3? COUNTER B 0 22222- 438 a PM) 148 PADH START" EHFFIATQ-THALH'S 235126 /215 1 8 SIGNALS ==wRnE ALL 0's TO WRITE FROM 1/0 cmcun 42 Dlt. 10, 1974 w, mwm Re. 28, Z65


$15220 Em E 32% 22: 2:5} m1 g 5% Wm E; 552E 3% 2 2 5; m2 2 2 E; 3 2K 8 a: o: T! a 532550 51 xx EE 1 525 $5 25% Ex 2 2% has, 1 a L: E Q 21 E w mm o 20 k V :35 E 2:2 .L g a: :58 wczu 6.5 PE; .21? mwv P5; to l 0 E E 535 a 52: E Z

J. W. IRWIN Dec. 10, 1974 ll Sheets-Sheet 9 ig'inal F1106 D86. 29, 1969 Q :30 2: :5 5Z2: 5:? s 02 mg m T E25 :2: E E5 5% E25: am 252m 3352: D2 am @555 $222 :2: i am a: 22 E 525 E 2%: 2: Es an gm :5 ea 5 a 0; E 2 55E 3 :2 a: z 2 2 Q5: 35: $2562 mac :2:

Due. 10, 1974 J. w. IRWIN Re. 28, 265

m'rammcoan nssmcnnomzuxonm DIGITAL-RECORDING SYSTEMS Original Filed Dec. 29, 1969 11 Sheets-Sheet 11 EN SE 3% I N 2m :25 ma ll|||. L 3 1 55235325 2w 1? 5523255 2 2 a 2 295032 nseozm llllr aseolmvff zs Q2 mseolmf fiasaoT NIIZZ::-w@ =s 232E coax:: :ii zzoccoaoo gc 522x25 s20lmvm zeol seolmqo$7 M; 235s: 2:::: :I: ;;OQQQQQQQQ QQ 522:5: oooooooo cooooo oZMQmMIQZf QO 22:5: 5222 5225 c a Q Q Q Q Q Q Q Q 4; 522 25 22: as: 92 E; QZEZE 25E 0? 0 m United States Patent 28,265 INTRARECORD RESYNCHRONIZATION IN DIGITAL-RECORDING SYSTEMS John W. Irwin, Loveland, Colo., assignor to International Business Machines Corporation, Armonk, N.Y. Original No. 3,641,534, dated Feb. 8, 1972, Ser. No. 888,766, Dec. 29, 1969. Application for reissue Feb. 4, 1974, Ser. No. 439,480

Int. Cl. Gllb 5/02 US. Cl. 36050 59 Claims Matter enclosed in heavy brackets appears in the original patent but forms no part of this reisme specification; matter printed in italics indicates the additions made by reissue.

ABSTRACT OF THE DISCLOSURE In a block of recorded data, resynchronization signals are interleaved among sets of sub-blocks of digital data signals for enabling reestablishment of self-clocking in a dead track. Resynchronization occurs within a block of recorded data. In a multitrack system, requiring the dead track in the skew buffers (SKB) is accomplished by placing the dead track SKB position at maximum leading relationship to the most lagging active track. If data signals from the previously dead track are received by SKB before the dead track has reached maximum lagging relationship, the previous dead track is activated for normal operation. Otherwise, the dead track is returned to dead-tracking status. The readout counter (ROC) of SKB controls read-back operations and determines signal format on the record media.

BACKGROUND OF THE INVENTION The present invention relates to moving magnetic media recording systems and, particularly, to a self-clocking resynchronization system and method for use within blocks of magnetically recorded data signals.

The design and method of operating magnetic record'- ing systems is usually a compromise between reliability and increasing data throughput. Users of magnetic recording systems often sacrifice throughput to decrease the number of permanent errors. Such reduction in permanent errors in the recording system for a given amount of data to be recorded has been accomplished by dividing the data into small blocks of recorded signals. Since, in present-day tape systems, a minimum spacing is usually provided between successive blocks of data, such approach not only reduces the available tape recording area in a given tape but also reduces the throughput of the system.

In higher density recording systems (1,000 bits per inch and more), it is practically a necessity that each track of data on a recording medium be characterized such that it can be self-clocking. The reason for this arrangement is that the cell in such a recording system is extremely short along the length of the media. Without self-clocking, data probably could not be successfully recovered. For successful self-clocking, it is desirable that the clock in the readback system be synchronized to the data as read from the tape every short distance of travel of the tape. To facilitate such resynchronization, it is desirable to have predetermined flux transitions occur in the recording at least once during a short length of tape. This can be accomplished either by inserting synchronization transitions between small sets of data signals or by utilization of a storage code having such transitions. The characteristics of such clock-synchronizing signals are such that the phase of the clock can be maintained, but that the frequency and phase-synchronizing and position-indicating 'ice components thereof are insufiicient to enable a clock that is out of synchronization to start proper operation.

The problems stated above are caused by present-day magnetic media recording systems having no facile method of resyncing within a block of data signals after a defect in the tape or lift-off has occurred; that is, after a signal has been lost from a given track. Such magnetic media recording systems continue in a degraded mode of operation; that is, without data signals from the defective (dead) track, throughout the remainder of the record block. Therefore, it is highly desirable that a magnetic media system should be able to resync within a block of data. To date, this has not been practical because, when data is recorded, there is a randomness of the recorded signal in accordance with information represented. Such randomness does not have predictable frequency and phase components nor precise position information such as to enable such resynchronization.

SUMMARY OF THE INVENTION It is the prime object of the present invention to pro vide high-density digital data recording in blocks of data having a capability of resynchronizing a dead track on-thefly within any block of such data.

A recording system using the present invention includes recording a set of data signals, then recording a set of resynchronization signals having predetermined signal phase and frequency-synchronizing and position-indicating components and repeating such recording steps until all data in one block has been recorded. Marker signals may be used to mark the boundary between the synchronizing and data signals, especially if the resynchronization signals are a valid form of recorded data.

A block of such recorded data is usually characterized by a preamble set of synchronization signals, a marker signal, then alternate sets of data signals, marker signals and resynchronization signals, and, finally, a postamble set of synchronization signals. The postamble enables reading the data block in a reverse direction. Padding signals may be added to one of the sets of data signals within the block such that all sets of data signals have the same number of digit positions or the same remainder when divided by the number of readout counter (ROC) states. The second method does not require padding in excess of the number of ROC states and therefore makes a more efficient use of the media. Marker signals may again mark the boundary between data signals and the padding signals within such sets of data signals.

A multitrack recording system usually has deskewing apparatus; that is, electronic circuitry capable of randomly receiving signals from a magnetic media wherein the signals from one track lead or lag signals from another track. The deskewing apparatus realigns the data into bytes for processing by other apparatus. According to a feature of the present invention, a dead track is resynchronized and requeued into the deskewing apparatus by artificially making the dead track position in a deskewing apparatus at maximum leading position. As data from the track being resynchronized is introduced into the deskewing apparatus, requeuing occurs. However, if the dead track position reaches maximum lagging position in the deskewing apparatus, the dead track may be returned to dead-track status until the next set of synchronizing signals is received. Then, resynchronization is again attempted. The interleaving of resynchronization signals with data signals within the data block not only provides for automatic resynchronization but also the requeuing of a dead track in a read-back system.

In a broad aspect of the invention, any suitable synchronization signal may be interleaved with data signals to enable the described resynchronization. To reduce costs, it is preferred that resynchronization signals interleaved with data signals have the same chracteristics and length as the preamble and postamble synchronization signals. Since many preambles and postambles are strings of ls or Us a specific feature of the invention provides resynchronization signals within a block of data as a string or burst of 1 or 0 signals. Bursts of any signal combinations may be used.

The present invention may be practiced either in a programmed general purpose machine (such as a microprogrammed machine), a completely hardware-provided set v of sequences, or a combination of the two. An example of a suitable microprogrammed control unit is the IBM 2841 microprogrammable control unit.

Another feature is the utilization of the deskewing counter (ROC) as a control counter in a recording system. Data addressing may be accomplished with this feature. Formatting of recording is based on an integral number of rotations (ROC cycles completely through all of its possible signal states in each rotation) of the deskewing counter. Symmetrical formatting is preferred for enhancing bidirectional reading. This format preferably includes symmetrically recorded resync signals. In this regard, the number of processed signal bytes is tallied for determining the length of a set of signals. ROC may be a part of such a counter.

In one form of the invention, resynchronization is based upon detection of resync signals written as bytes in plural tracks on the recording media. The resync signal then has a length of not less than twice the maximum compensable skew in the recording system. When the resyn signal in each track provides track position information independent of similar signals recorded in other tracks, the resync signal need not be such length. Requeuing of the previously dead track in the deskewing apparatus of the system may use those features of the present invention; for

example, making the dead track effectively appear as the most leading track at the onset of resync attempts while the most lagging at the extreme end of an unsuccessful resync attempt.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified diagrammatic presentation of a single track of data recorded in accordance with the teachings of the present invention. The illustrated format facilities reading in either direction and provides intrablock resynchronization in either direction of reading.

FIG. 2 is a simplified block signal diagram of a magnetic tape system utilizing the teachings of the present invention.

FIGS. 3A and 3B show a simplified program/hardware operation flow chart used to record a block of data in accordance with the teachings of the present invention and is used to describe the recording operation of the FIG. 2 illustrated apparatus. These figures are referred to generally as FIG. 3.

FIG. 4 is a simplified program/hardware operation flow chart of a read sequence used to read back and resynchronize a dead track in accordance with the teachings of the present invention.

FIG. 5 is a simplified program/hardware operation flow chart showing detailed read-back resynchronization operations usable with the operation set forth in the flow chart of FIG. 4.

FIG. 6 is a simplified signal flow diagram of a start and cycle portion of the FIG. 2 illustrated apparatus.

FIG. 7 is a simplified signal flow diagram of a write resynchronization circuit usable with the FIG. 2 illustrated apparatus.

FIG. 8 is a simplified signal flow diagram of a read resynchronization and terminate circuit usable with the FIG. 2 illustrated apparatus.

FIGS. 9 and 10 are diagrammatic representations of deskewing with read-back signal information contents and selected control signals during a resyncing operation of a dead track, respectively, for trailing or lagging and leading dead tracks.

FIG. it illustrates a resync signal having a pattern of 1s and 0s in a run-length limited recording code.

FIG. 12 is a simplified diagram of an ROC rotation controlled data location feature of this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now more particularly to the drawings, like numerals indicate like parts and structural features in the various diagrams. It is to be understood that the illustrations of signal flow diagrams and the operation flow charts are to be interpreted as including functional representations of microprograms in a general purpose programmable machine usable to accomplish the functions and operations described herein. Since programmable machines can take various forms and are well known and the programming of same to accomplish the described functions can be varied, no detailed description of a particular program is included. A programmer of ordinary skill can construct a program for practicing the present invention based upon the operation flow charts.

RECORDING SCHEMES It is well known that there are many types of systems for recording digital data, particularly on magnetic media. The present invention may be practiced with any form of recording on any media. While techniques of recording in various recording systems may vary somewhat in accordance with the characteristics thereof, the implementation of this invention may be varied to accommodate such variations. For example, synchronization signals usable with various recording systems may vary somewhat in accord- Phase encoded recordings usually utilize synchronization signals consisting of bursts of recorded 0's. Padding within a data block to make the length of the data block a predetermined number of signals or digit positions consists of a string or burst of recorded ls. Phase encoding is well known, and the signal representation of 0s and 1's is likewise known. On the other hand, variations of such phase encoding may utilize bursts of 1s for synchronization signals and bursts of 0s for padding in a data block.

US. Pat. No. 3,217,183, issued to L. H. Thompson et al., describes a variation of phase encoded recording. Another reference of interest is an article by R. C. Franchini on page 112 of the IBM Technical Disclosure Bulletin, July 1967.

In most magnetic-recording systems, the recording of data occurs only in one direction of tape motion. In accordance therewith, there is a beginning or end to each data block. Synchronization signals disposed at the beginning and end of the block, respectively, are termed the preamble and postamble. However, in many magneticmedia systems, reading can occur in both directions.

Another recording scheme is NRZI in which a flux transition on the record represents a binary 1 and no flux transition a binary 0. In NRZI recording, the record is divided into cells each capable of. recording one bit of binary data. Synchronization signals in NRZI recording are a burst of ls. For self-clocking purposes, an additional clock-synchronizing signal may be periodically recorded among the data signals.

The recording schemes described above, as well as other recording schemes not described herein, can be modified by limiting the sequence (nm) of recorded signals to predetermine maximum lengths of ls or Us or both. In such systems, the data to be recorded is converted into a storage code usually containing a greater number of signals than is usually used to represent a byte of data. For example. seven hits of data received by a recording system can be converted into a set of eight signals. The characteristics of the eight signals are predetermined such as to limit the bandwidth of the recording signals, (i.e., the maximum number of 1s or 0s in a string). It also may require that flux transitions of a certain character occur at least once in a small number of cells. The usage of such predetermined fiux transitions will be described later. It is known that the conversion of data representable by such run-length limited codes enhances the recording and readback in magnetic-media systems. The utilization of storage codes as substitutions for dataprocessing codes can be successfully used in practicing the present invention.

As used herein, the words write" and record" are interchangeably used to designate recording signals on a storage media. Similarly, the words read, read back, and sense are interchangeably used to designate recovery of recorded signals from a storage media and conversion to appropriate digital signals.

RECORD FORMAT FIG. 1 diagrammatically illustrates one track of a multitrack block of data recorded in accordance with the teachings of the present invention. It is understood that any suitable recording scheme may be utilized in this format. For purposes of discussion only, it is assumed that phase-encoded recording, described in U.S. Pat. No. 3,217,183, is used with synchronization bursts of ls with padding bursts of 0s. The forward direction of tape movement is assumed to be from right to left. Therefore, the beginning of the block of data is at the lefthand edge of FIG. 1.

The recorded block of data signals in each track includes preamble 10 consisting of a synchronizing burst of signals B. The block is concluded by a similar set of synchronizing signals B in postamble 24. Intermediate the preamble and postamble are interleaved sets of data signals D, marking signals M, and resynchronization signals B. Data signals are grouped in sets 12, 16, and 22. The interleaved resynchronization signals B are grouped in resynchronization sets 14 and 20. These latter signals enable resynchronization of a dead track within a block of data signals. It is understood that the number of sets of data signals and the interleaved resynchronization signals is a matter of design choice. Identifying the boundaries between the preamble, postamble, data signals, and the interleaved resynchronization signals are a plurality of marker signals 11, 13, 15, 17, 21, and 23. The recording of the illustrated block of signals begins from the left and proceeds toward the right in accordance with known techniques. The burst of signals are simultaneously recorded in all tracks. Defining one byte as being one cell in each track across a magnetic tape, a burst signal is all 1s in a byte. Marker signals are similarly constructed of all ls and all 0s in a plurality of bytes. The ensuing discussion for the most part is directed at a single track in a multitrack record.

It is desired, as will become apparent, that the number of bits recorded on the tape or other media between the beginnings of successively occurring sets of data signals be the same or have the same remainder when divided by the number of ROC states. It is preferred all such spacings be identical except the last spacing in a block which may be truncated. That is, the number of bits between the trailing edge of marker signals 11, 15, and 21 should be identical or have the same remainder when divided by the number of ROC states. This spacing is represented by double-ended arrows 26. The length of the set of data signals 22 is not important msofar as reading from left to right is concerned. However, in systems where reading occurs in both directions of tape motion, the length of data set 22 is important for maintaining the relationship between postamble 24 and marker signal 17 the same as the relationship between marker signals 13 and 17. As will become apparent, such consistency in spacing reduces costs in read circuits. At the end of a data block, it is quite difficult, it not imall) possible, to always ensure that the number of data signals 22a within set 22 will fill all the predetermined number of digit positions (for example, 1,024). To make the remainder when data set 22 is divided by the number of ROC states the same as the other data sets 12 and 16, a subset 22b of padding signals P are added. Such signals P are either a strong of Us or a string of 1s in accordance with the definition of the recording system. For convenience, marker signal 23 is disposed between subset 22a of data signals and padding signals in subset 22b.

The illustrated format of tape recording enables resynchronization of a dead track as well as the requeuing of a reactivated track in a multitrack system within the block of data signals. Later, a more detailed format and circuit timing relation is defined in Table I. It is not necessary to continue dead-tracking throughout the block of data signals, thereby permitting a longer block of signals to be reliably recorded and reproduced than heretofore was generally practiced.

Preamble 10, postamble 24, and synchronizing signals B are strings of is Similarly, the interleaved resynchronization signals B are strings of 1s. For simplicity, all bursts of signals B should have the same length and characteristics. The end of preamble 10 is indicated by marker signal 11. All marker signals used in the first-described embodiment have two bytes respectively having all ()s and ls recorded therein at the beginnig of a set of data signals and all ls and Os recorded therein at the end of a set of data signals. Therefore, the beginning of the block of data consists of a string of ls in preamble 10 and a 0 and a 1 in marker signal 11.

Data signals D are any mix of l and Us or may be permutation codes. Each set of data signals may be of any predetermined length. In one constructed embodiment of the present invention, each set of data signals was arbitrarily selected as containing a maximum of 1,024 cells or digit positions per track, or l,024 bytes of data in a multitrack record. The last set of data signals 22b may contain fewer than 1,024 as will become apparent.

Reproducing the recorded data signals D, shown in FIG. 1, may be accomplished by reading in either direction. In reading from left to right, preamble 10 is first read to synchronize the self-clocking read-back circuits. Upon detection of marker signal 11, the read-back circuit establishes a predetermined count (1,024) for counting data signals from set 12. Data signals 12 are then read. Upon detection of marker signal 13 and the completion of the predetermined count, the read-back circuit discontinues sending data signals and prepares to read set 14 resynchronization signals B.

Such a read operation (reading a set of data signals and a set of resynchronization signals) is repeated until either the detection of postamble 24 or receipt of a stop read signal from control circuitry (not shown). If the illustrated track had been deadtracked (i.e., the signal envelope of the read-back signal fell below an amplitude threshold or a phase error was detected), the read-back circuitry normally would automatically ignore any signals received from such track. By use of error correction codes, the dead-tracking can be compensated for in some instances in a control unit, which is not the subject of the present invention. However, in reading back the format illustrated in FIG. 1, the sets of resynchronizing signals are utilized to resynchronize the channel clock within the block of signals. If resynchronization is successful, the next-occurring set of data signals is read. Therefore, the dead-tracking function can be aborted within the block of data by an interleaved set of resynchronizing signals B. Upon detection of a marker signal, the readback circuit is activated to read the next-occurring set of data signals.

Also, in magnetic tape recording, it is desirable to have expansion space in a block of data. Padding signal 22b can provide such expansion without subsequently altering the length of a data block. It is also understood that such padding signals may be inserted in any of the sets of recorded data signals for permitting growth of the record anywhere within the data block.

In the FIG. 1 illustration, marker signal 23 being all ls across the tape followed by all Os across the tape, is efiectively extended by the padding 0 signals. The last padding 0 abuts the first 1 signal in postamble 24. There is no need for a marker signal at this point because the 0-] change signifies the beginning of postamble 24.

Reading in the reverse direction is Substantially identical to the forward direction. Marker signals 23, 17, and 13, respectively, signify the ends of sets of recorded data signals. A ditference arises in that for deskewing, the later-described read-in counters (RIC) for the various record tracks are initiated at the 1-0 change between postamble 24 and padding signals P. This establishes a fixed relationship between the state of the ROC and marker signal 21. Such action is more fully described later. If the counters are always in the same signal state upon the reading of such marker signals, the first occurring L data signal (i.e., the first cell being scanned) may always be loaded into the same relative position in the deskewing apparatus. his simplifies deskewing and the control functions related thereto. It also facilitates requeuing a dead track in accordance with teachings of the present invention. The reasons for such simplification need not be delved into for purposes of understanding the present invention.

GENERAL DESCRIPTION FIG. 2 is a simplified illustration of a magnetic-tape subsystem using the teachings of the present invention and connected through communications channel 30 to utilization means, such as a central processing unit (not shown). The subsystem, as usual, has a plurality of tape handlers 31; only one of which is activated for reading or writing at a given time. Tape control system 32 selectively couples one of the tape handlers 31 to channel 30 such that data can be recorded on or read from a magnetic tape (not shown) being processed. The invention is illustrated by certain portions of such tape control; those certain portions being accented. It is understood that many other control circuits are necessary to the successful operation of a magnetic-tape subsystem; such other control circuits are diagrammatically illustrated by box 33 labeled OTHER TAPE CONTROLS (OTC). Such OTHER TAPE CONTROLS (OTC 33) include motion controls. ON and OFF controls for the respective tape handlers, and the like. Signals for effecting such other control functions are exchanged between OTC 33, channel 30, and tape units 31 over cables 34 and 35.

Some control signals intimately associated with the practice of the present invention are now described. First, two control signals supplied from channel 30 are described. A COMMAND OUT (CMD OUT) signal is supplied over line 36 from channel 30 to tape control 32. CMD OUT initially sets up OTC 33 in a read or write operation. Signals termed command are sent to OTC 33 along with CMD OUT for conditioning OTC 33 to perform certain functions. CMD OUT sent during performance of a given function indicates to tape control 32 that no more tape functions are desired. In a read operation, such a CMD OUT is interpreted as do not send any more data to channel 30 from the activated tape handler 31. In a record or write operation, such a CMD OUT indicates there is no more data to be recorded. The latter two instances of CMD OUT are the only ones referred to herein.

A SERVICE OUT (SVC OUT) signal, supplied over line 37 to OTC 33 during a read operation, indicates that channel 30 has successfully received one byte of data supplied from a tape handler 31. During a write operation, SVC OUT is interpreted as indicating that data to be recorded is now available from channel 30.

Control signals are also supplied from tape control 32 to channel 30. Many of these are indicated by cable 35.

A control signal of interest to the practice of the present invention is the CHANNEL SERVICE IN (CHL SVC IN) signal supplied over line 38a. This latter signal is initiated by OTC 33 and supplied through start-and-cycle circuit 52 for reasons that will become apparent. In a read operation, CHL SVC IN signal indicates that one byte of data has been read from a tape in tape handler 31 and is available to channel 30. During a write operation, CHL SVC IN is a request for channel 30 to supply the next byte of data to be recorded. Upon supplying same, channel 30 supplies a SVC OUT control signal indicating that such byte of data is available or CMD OUT for stopping the write operation.

These just-described signals are shown as being received through OTC 33. While those control circuits are not described in detail, the ensuing detailed description of tape control 32 and known tape control circuits will make the means effecting such exchange apparent.

Data flow between an activated tape handler 31 and channel 30 is via the buffer registers 40. Buffer registers 40 include deskewing apparatus 49, as later described. In a read operation, data sense-and-detect circuits 41 (one circuit for each record track) receive signals from one of the respective tape handlers 31 and supply digital data signals to butter registers 40. Such signals, while not yet deskewed, are in digital form. Data sense-and-detect circuits 41 include self-clocking circuitry necessary for the successful readback of high density magnetic records. Also included are amplitude and phase threshold circuits for detecting whether or not recorded data signals are being successfully recovered from the tape being processed. Such circuits are well known and will not be further described for that reason.

Data flow during a write operation is from channel 30, through the buffer registers 40, thence to write circuits 42 (one circuit for each record track). Write circuits 42 convert the received digital signals into the appropriate recording waveforms in accordance with the selected recording scheme and supply same to the activated tape handler 31 for recording on tape. Write circuits 42 may include a set of final amplifiers with the actual recording signals being distributed directly to the recording transducers of any tape handler 31 over a Write bus.

Data signals to be written on a tape in a handler 31 are supplied to I/O register 48 in buffer registers 40. Suitable gating control circuits (not shown) gate the signals directly to write circuits 42 for a recordation on a magnetic tape. The one exception to this statement is described in detail later. All of the other registers shown within buffer registers 40 are used in the read-back operation. The digital signals being processed during a read operation are first supplied to deskewing apparatus 49. Such deskewing apparatus is well known in the art. For example, a deskewing system using a read-in counter (RIC) 43 for each track and a single readout counter (ROC) 44 is described by Floros in US. Pat. No. 2,921,296. RlCs 43 keep track of the digital signals as they are received from data sense-and-detect circuit 41. When all RICs 43 have proceeded from a predetermined signal condition, one byte of data has been aligned and is ready to be transmitted to channel 30. At this time, ROC 44 is altered by one count and, simultaneously therewith, one byte of data is transferred to error register 45. In error register 45, error detection and correction functions are perforned. Such functions are not a part of the present invention and, therefore, will not be further described. From error register 45, the byte of data is transferred to read I register 46, thence to read 2 register 47 and read 3 register 55. The number of these registers is a design choice made with respect to timing. From read 3 register 55, the byte of data is supplied to I/O register 48. If the read-back circuitry of FIG. 2 is currently reading back data signal D, a CHL SVC IN signal is supplied to channel 30 to indicate that I/O register 48 has one byte of data available for transfer to channel 30. When reading resynchronization signals B, the CHL SVC IN signal is never sent to channel 30, hence resynchronization signals are obliterated as new signals are received.

The description of FIG. 2 up to now has concerned itself with prior tape control devices. The additional circuits used to implement the present invention in the FIG. 2 illustrated control include read resync circuits 50, write resync circuits 51, and an illustrative modification of the sequence control of OTC 33 is set forth in start-and-cycle circuits 52. It is to be understood that some of the individual functions performed and circuits illustrated in these latter three circuit configurations may have been found in prior tape control units. However, the functions performed by these three circuits and the interconnections therebetween and with the other portions of the tape subsystem as set forth in the later-described fiow charts illustrate how the invention can be practiced. An understanding of the detailed connection illustrated in FIG. 2 will become apparent from the descriptions of the three circuits. Generally, OTC 33 and start-and-cycle circuits 52 initialize the control unit and respond to the recorded signals for detecting the resynchronization bursts, for inhibiting transfer of such resynchronization signals to channel 30, and respond to a CMD OUT signal for stopping operations. Read resync circuits 50 control resynchronization of a dead track and requeue such dead track into the deskewing operation performed by deskew apparatus 49. In this conection, read resync circuits 50 have a close interaction with the deskewing operation and data senseand-detect circuits 41. Write resync circuits 51 program the operation of the tape system such that resynchronization signals are properly written between sets of data signals being recorded.

FORMAT-TO-SYSTEM RELATIONSHIPS Before proceeding into the description, the format relationship of data signals on the most lagging track on the tape with the readout counter (ROC), the burst counter, and the byte count is described with respect to Table I. The RIC of the most lagging track determines the ROC count; therefore, the one most lagging track only is considered. In the Table, D indicates data signals and may be either a zero or a one, C indicates a check digit, M indicates a marker signal which may be either all zeros or ones in accordance with the previous discussion. The relationhip of s and ls for the illustrated embodiment is shown in parenthesis under the MM designations. Numbers are counts in the respective counters.

The burst counter, used during write operations, to record or write a resync burst is shown in FIG. 7. When the burst count is equal to l, a check digit (CRC) is transferred for recording; when equal to 2 and 3, the marker signal is written (i.e., all ls then all US). In steps 4 through 31, 28 all 1 bytes" are written. In burst count steps 32 and 33, the marker signal consisting of all Os then all ls is written. In step 34, writing of data is reinitiated. The byte count is shown as a decrementing count. The last data byte is B=0, which corresponds to ROC in the forward direction of equal 14. At the right-hand edge of Table I, the byte counter is shown as being set to 1,024 at the first data byte and decremented to 1,023 at the second data byte.

In observing Table I, it should be remembered that the data byte aligned with ROC forward=l4 does not reach I/O register 48 until several cycles of ROC. That is, ROC 44 counts the data bytes as they are transferred from SKB 49 to read 1 register 46. That data byte will not reach the I/O register until ROC=3. Check digit does not reach I/O register 48 until ROC forward=4. Therefore the SVC IN signal to channel 30 is not forwarded from control unit 32 until after ROC 44 has reached a count of at least 5. Then SVC OUT is received from channel 30. This is an important point to remember in considering the timing of the resync bursts and the read resync cycle illustrated hardware embodiment.

RECORDING Recording signals on a magnetic tape using the present invention are first described. Generally, there are two approaches to recording in accordance with the present invention. The first approach is to write a number of data signals D within a block of data signals without knowing beforehand the total number of data signals to be recorded. The first approach is described in detail with respect to FIGS. 3 and 7. The second approach is to write a predetermined number of data signals to form a block of such data signals having interleaved resynchronization signals. The second approach is described generally later as a modification to the first approach. Because all recordings can be efi'ected without knowing beforehand the number of signals to be recorded, the first-mentioned approach is described in detail. For purposes of discussion, in both approaches, it is assumed that one byte of data is recorded across the tape at a time. The byte of data may consist of eight binary digit positions plus parity. The parallel re- TABLE I Signals D C MG) Mtu) 1. .1 1 1 1 1. 1 him) MU] D D Burst counter l 2 3 4 16 17 18 19 31 32 33 34 ROC forward." 14 15 0 1 2 13 14 15 U 1 13 14 15 0 1 ROC backward t) 15 14 13 12 1 0 15 14 13 1 0 15 14 Byte count 0 0 0 0 0 0 0 0 (l 0 0 0 0 1,024 1,023

The write and read-back systems are designed such that ROC will pass a reference count at predetermined points of the recording within the data block. It is to be appreciated that ROC changes from 15 to 0 several times while reading data. However, upon the onset of a set of data signals, ROC should be moving from 15 to O in either direction of reading. As shown above in the forward direction which corresponds to reading Table I from left to right, ROC changes from 15 to 0 upon detection of the marker signal at the trailing end of the all ls resync burst. The resync burst contains 28 ones such that the marker signals plus the resync burst corresponds to two rotations of ROC. At the right-hand edge of Table I, it is seen that ROC in the forward direction changes from 15 to 0 when reading the trailing end marker signal, as desired. In the backward direction, the marker signal ROC count relationship is somewhat dilferent because of the check digit in the data subset. Leaving the resync burst, which is now the left-hand side of Table I, ROC=15 at the check digit and goes to 0 for the first-encountered data byte.

cording of such a byte requires one cell in each of nine data tracks.

To record an unknown number of data signals and ensure there is data available to be recorded, it is desirable for the tape system to first obtain one byte of data to be recorded from channel 30 before the tape motion in a handler 31 is initiated. Therefore, in preparing for recording, control 32 requests the first byte of data before initiating motion of the tape. Referring to FIG. 3, the first step in the program/hardware sequence flow chart is to make available one byte of data to be written. As soon as one byte of data is available, a motion control signal is issued by OTC 33 over cable 34. When the tape has reached operating velocity, an indicating signal is supplied over cable 34 to OTC 33. Preamble 10 is then written by repeating steps 61 and 62. In step 61, write initial sync burst signal (one signal B in a burst of such signals B) is written in each track on the tape. In step 62, the number of signals B actually written in each track is compared with the number desired to be written in preamble 10.

1f the count is not complete, operation is returned to the input of step 61. When preamble count is complete, operation proceeds to step 63 to write one marker signal.

The marker signal in the illustrated embodiment consists of writing all Os across the tape, followed by writing all is across the tape. Any form of marker signal, of course, can be used. Next, in step 64, the byte of data made available in step is transferred to write circuits 42. According to step 65, as the byte is transferred, a later-described byte counter in start-and-cycle circuits 52 is activated to tally the number of recorded bytes. This tally is used to determine the size of sets of data signals.

Then, in step 66, the write data cycle in start-and-cycle circuits 52 is initiated. At this time, the CHL SVC IN signal is forwarded to channel 30 enabling another byte of data to be transferred to I/O register 48. In this discussion, it is assumed that the transfer rate of channel 30 is much higher than the recording rate in tape handler 31. Therefore, the data signals to be recorded are available in l/O register 48 substantially simultaneously with the transmittal of the CHL SVC IN signal.

The writing of one set of data signals is completed by the next loop of steps 67 through 71, inclusive. If 1,024 digit positions occur in each track, then 1,023 bytes of data are recorded by such loop cycling itself 1,023 times. Remember, one byte has already been recorded. In step 67, one byte is transferred from I/O register 48 to write circuit 42 for recording. In decision step 68, the receipt or nonreceipt of a CMD OUT signal is sensed.

If the CMD OUT signal has been received, further writing is stopped and a write termination operation, later described, is initiated. If no CMD OUT signal has been received, the write operation proceeds to decision step 69. In step 69, a test for receipt of the SVC OUT signal is made. If it has not been received, no data is available H from channel 30. Steps 68 and 69 are repeated until SVC OUT is received. Normally, the wait for a SVC OUT signal is short. As soon as SVC OUT is received, in step 70 the byte counter in start-and-cycle circuit 52 is altered by unity. Then, in decision step 71, the byte counter is sensed to see whether or not the byte count is complete (i.e., whether or not 1,024 bytes have been recorded). If the count is not complete, the sequence is repeated. If it is completed, then during step 73 the last byte of data is transferred to write circuit 42. This means that, in decision step 71, a byte count of 1,022 is tested with the last byte being Written during step 73, making a total of 1,024 bytes. In many recording systems, it is desired that a longitudinal (track) or cyclic redundancy check di it (CRC) be recorded. This recording occurs during step 74. This check digit may be one byte across the tape between the last data signal and the marker signal 13, for example.

The write operation in steps 75-82 then writes marker signal 13 and set 14 of resynchronization signals B. Before initiating the writing of the first resynchronization signal, in step 75 the receipt of CMD OUT is again tested. If CMD OUT has been received, a write termination operation is initiated. If a CMD OUT signal has not been received, then the receipt of a SVC OUT signal is sensed during step 76. It is remembered that before data is initiated to be written, it is desired to have one byte of data in register 48. This is the purpose of testing for the receipt of a SVC OUT and not initiating further operation until SVC OUT has been received. As soon as SVC OUT has been received, during step 77 a marker signal, such as marker signal 13 (all 1's then all Os), is written. Immediately after writing the marker signal, STOP is sensed during step 78. If STOP is on, then postamble 24 is written, as will be later described. If STOP is off, resync burst 14 is written in steps 80 through 82. In step 80, one signal B is written in one cell position of each track. Then, during step 81, STOP is again sensed. If STOP is off, which would be the case in writing a resync burst, in step 82 the tally of the recorded signals B is sensed. If it is desired to write 24 signals in a burst, then the loop 80, 81, and 82 is repeated until the tally has reached 24. At that time write operations return to step 63 (FIG. 3A), which writes marker signal 15. Then, the above-described cycle for writing a set of data signals is repeated. The above-described operations of alternately writing data signals and burst of resynchronization signals are repeated until CMD OUT is received, at which time the writing operation is terminated. Termination includes recording padding signals P in data set 22 and Writing postamble 24.

Because of the nonpredetermined length of data to be recorded, a CMD OUT signal for terminating the write operations can be received at any time. For this reason, CMD OUT is sensed in steps 68 and 75. In step 68, the CMD OUT is sensed while Writing a set of data signals. If a CMD OUT has been received, the Write operation is terminated. First, a check digit must be written. To set up the appropriate sequences, in step 86 a later-described resync burst counter is set to 1. This action enables a sequence to write a check digit in step 74. Since CMD OUT has already been set, the operation branches to step 87 which sets a stop latch in start-and-cycle circuit 52. This action indicates that STOP is on. Marker signal 23 (all ls, then all Us) is written during step 77. In step 78, since STOP is on. deceision step 88 determines whether or not the byte count has been complete (i.e., whether the correct number of positions have been used to complete data set 22). Such correct number is any number which is an integral multiple of the ROC modulus. 1n the present illustration, such correct number is an integral multiple of 16, the number of ROC 44 stable states. If the byte count does not bear the correct relationship to the number of ROC states, the byte count is altered by unit in step 89 and then step 78 is repeated. This small sequence loop is repeated to complete the byte count. This action writes all 0 padding bytes.

The operation proceeds to step 80 in which one postamble signal B is written. Since padding signals are (is and burst signals B are ls, the end of the block is indicated by the 0 to 1 transition. With no 0 padding signals, the all Os byte of marker signal 23 is the last all 0 signal in the data block. Then, in decision step 81, STOP being on, the operation goes to END ls (postamble) count decision step 90. The postamble count is preset in step 86 such that a set number of bursts of signals B are written in repeated steps 80. The number of postamble all ls bytes may be designed into the later-described hardware or be programmed. The postamble count is altered (incremented) in step 92 in each repetition. Upon the completion of the postamble count, the flow chart is exited at line 91 to terminate the write operation in a known manner.

READING The sequence of operations for reading recorded data in the format shown in FIG. I is now described. It is assumed that the tape is moving and the read circuits have been initialized; that is, the read circuits are all activated to the proper condition and awaiting the detection of a block of data. Upon the detection of readback signal envelopes by data sense-and-detect circuits 41, the read operation is initiated in step of FIG. 4. Step 100 is not completed until preamble 10 or postamble 24 has been read. This completion is detected by sensing an all Os byte in marker signal 11 after reading the burst of all ls bytes. The first decision is performed in step 101, wherein the direction of read is determined. If the read is in a forward direction, padding signals 22b need not be eliminated from the read-back; therefore, the read operation goes immediately to decision step 102 which detects when ROC 44 has a state equal to 5. This state corresponds to the first byte of readback data having progressed through bufi'er registers 40 into I/O register 48. The number 5 is derived from timing con- 13 siderations. Other hardware designs would alter the state of ROC 44 at which the read sequence is initiated. In any event, when the ROC 44 has reached a predetermined state, a read sequence is initiated, indicated by line 103.

However, if the reading operation is in the backward direction, decision step 104 is first performed. This step detects marker signal 23. If no marker signal has been detected, padding signals 22b are being read. During this cycling, the byte count is altered in step 109 and there is no transfer of signals to channel 30. The read-back padding signals are transferred into read-1 and read-2 registers 46 and 47 for the detection of marker signal 23. After the detection of marker signal 23 in step 105, a check digit is transferred to error detection circuitry (not shown). It will be remembered that the last item Written in any set of data is a check digit. Therefore, when reading in the backward direction, the first data to be encountered is this check digit. Step 106 is a two-cycle delay such that the first byte of data signals D, following the H marker signal in registers 46 and 47, is transferred into I/O register 48. Upon the completion of delay in step 106, the read sequence is initiated, indicated by line 103.

Detection of marker signal 23 may also be accomplished within data sense-and-detect circuits 41. This approach is followed in the later-described hardware embodiment. Generally during a backward read operation, detection of a first occurring 1 signal after detection of a signal indicates marker signal 23. The leading track then establishes detection of marker signal 23.

The first step 107 in read operation sets a steering latch in start-and-cycle circuit 52. This latch being set signifies the beginning of a read operation and enables circuit 52 to cycle until one set of data signals is read. In step 108, one byte of data is read. This means that one byte of data is transferred from deskewing apparatus 49 to the error detection and correction register 45 under the control of ROC 44. During the same step, the byte counter in start-and-cycle circuit 52 is altered by unity. When reading set 22 of data signals, the byte count includes padding signals P.

During decision step 110, the status of the byte counter is sensed. If the byte count is complete, and of a data set is indicated; reading data is terminated, and a read resync cycle 111 is initiated. Read resync cycle 111 is described later with respect to FIG. 5. This cycle enables the automatic resyncing of a dead track and inhibits the transfer of resynchronization signals B through I/O register 48. It is also used to terminate a read operation. If the byte count is not complete, decision step 112 is initiated. If a marker signal is detected, end of data is indicated and the read resync cycle of FIG. is initiated. Only if no marker signal has been detected and the byte count is not complete is step 103 reinitiated and repeated until one of the two end of data conditions is met.

The initiation of the read resync cycle of FIG. 5 includes resetting steering circuit in step 116. The direction of tape motion is again detected in decision step 117. If tape motion is in the forward direction (i.e., from left to right in FIG. 1), a check digit (CRC) is transferred to an error detection and correction circuit in step 118. If the reading is in the backward direction, the check digit has already been transferred, and the operation proceeds directly to decision step 119. This decision step determines the state of ROC 44. Before a resynchronization burst can be read, all data must have been transferred from I/O register 48 to channel 30. In the illustrated hardware design, the last data byte resides in I/O register 48 when ROC: l2. Returning now to the forward direction reading, after the transfer of the check digit, the condition of ROC 44 is checked in decision step 120. In the particular embodiment, when ROC=4, everything is appropriate for entering step 119. If, however, ROC 44 contains any number but 4, the read operation is stopped. In the illustrated embodiment, the check digit should be transferred when ROC 44:4. If operation is ditferent, either the data set being read is the last data set in the block and contains less than 1,024 bytes, or a fautly read operation has occurred and should be stopped. Control circuits in OTC 33 determine which is the case by measuring the length of the remaining data signals and setting an error latch (not shown) if the termination was premature.

Upon detection of ROC 44:12, the read resync operation is initiated by setting a phase or resynchronization test for dead track in step 121. This setup enables testing whether or not the dead track has been resynchronized at that point in the resynchronization burst. In decision step 122, deskewing apparatus 49 has been stepped to reference state ROC=15. In the illustrated deskewing apparatus there are 16 deskewing positions corresponding to ROC=0 through ROC=15. Change from ROC=15 to ROC=0 is arbitatrily defined as a reference change. For requeuing a dead track into deskewing apparatus (SKB) 49, the apparatus should be in a well defined operational state. Control 32 is cycled until this condition occurs. In step 123, the requeuing of the dead track into deskewing apparatus 49 is set up. This action activates circuitry or programming for detecting the successful readout of a present dead track into deskewing apparatus 49. In step 124, ROC 44 is cycled until it reaches state 14. This signal state corresponds to a predetermined number of resync bytes of all ls being transferred through deskewing apparatus 49. During the delay, the dead track is hopefully resynchronized and made ready to be reactivated. The number of resync signals processed corresponds to the length (16 bytes) of deskewing apparatus 49.

The next step in the flow chart is to test the success of the resynchronization of the dead track. In step 125, a test circuit is activated. In decision steps 126 through 128, the test is repeated throughout the resync burst being read. In step 126, a test is made of whether or not at least three tracks are not supplying satisfactory signals. In case three tracks are not supplying satisfactory signals the reading operation is aborted. Such a condition indicates either end of a data block or readback is entirely unsatisfactory. If, however, less than three tracks are supplying no signals, decision step 127 is initiated. The test is whether any RIC 43 has a value of 13. This magnitude corresponds to the detection of the maximum skew in the illustrated read-back system. If none of the RICs have a value of 13 in decision step 128, there is a test made of whether or not an ROC step to 0 has been initiated. If no ROC step to 0 has been initiated, steps 126, 127, and 128 are repeated. ROC 44 stepping from 15 to 0 indicates successful readback from the previously dead track. That is, one byte of signals has been assembled into SKB 49. The occurrence of any RIC equaling 13 is an indication that the dead track has not provided signals to deskewing apparatus 49 (i.e., maximum skew has been exceeded). This relationship is described later with respect to Table I and FIGS. 9 and 10. Therefore in step 129, dead-tracking of such dead track is reinitiated. If an ROC step to 0 has been initiated in decision step 128, a successful resynchronization of the previously dead track has occurred. Of course, it must be remembered that, if there are no dead tracks, step 128 is performed immediately. This completes the read-back of a resynchronization burst.

Next, the read-back circuitry is conditioned by reenter read sequence 130 for reading the next set of data signals. In decision step 131, the direction of tape motion is again detected. If the motion is in the forward direction, decision step 102a, which corresponds to decision step 102 of FIG. 4, is performed. If it is in the backward direction, steps 132 through 134 are performed. In decision step 132, the condition of ROC 44 being equal to 4 is sensed. In step 133, a check digit is transferred to the correction circuitry in the same manner as in step of FIG. 4. In decision step 134, there is a waiting period until RO C 44:6. Normally, it will be equal to 6 since the transfer of check digit in step 133 takes one cycle and advancing the first data byte to the I/O register will take one cycle. Upon completion of steps 102a or 134, the read sequence is reinitiated by performance of step 107 in FIG. 4. The above-described sequences are repeated until the detection of the end of the block of data. This may be accomplished in decision step 126 (FIG. wherein more than three tracks do not supply a read-back signal.

The abovedescribed flow charts of operations can be implemented by programming, hardware sequences, or a combination of both. A simplified illustration of a hardware implementation of the flow charts is described. The description of the hardware will be keyed to the flowcharting for a clearer understanding of the illustrated embodiments.

WRITE HARDWARE Write operation hardware is described with particular reference to FIGS. 2, 6 and 7. The description assumes that the usual control signals have been transferred through channel 30 to OTC 33 for initiating a write operation. OTC 33 is supplying a continuous control signal on line 135 indicating a write operation is being performed as well as supplying a periodic write clock signal (pulse) on line 136. In a practical embodiment, the write clock pulse is derived from a single source and within OTC 33 divided into a plurality of separately timed pulses. This approach is one of known design choice used to avoid pulse overlapping problems, other critical electrical signal-timing problems, as well as reducing the number of circuits in control unit 32. For purposes of understand the present invention, it is unnecessary to delve into such engineering design niceties. Further, for simplicity, the actual connections are not shown but are understood to be made be tween the various figures. In FIG. 6, preamble control 137 is first activated by OTC 33 to write-preamble of FIG. 1. This corresponds to performance of steps 61 and 62. Action is initiated by the write clock, the write signal, SVC OUT signal indicating that one byte of data is available, as in step 60, and start pulse on line 138. Preamble 10 is written as preamble control 137 supplies a write-allls signal over line 148 to write resync control 51. Control 51, in turn, supplies a write-all-ls signal over line 149 to write circuit 42. Upon completing writing the preamble, preamble control 137 writes marker signal 11, as set forth for step 63. It is recalled that this consists of writing an all Os byte across the tape and then writing an all ls byte. An Os signal is supplied over line 188 followed by a write-all-ls signal supplied over line 148 to write resync circuit 51. Circuit 51 transfers these signals over lines 149 and 189 to write circuit 42. Since recording preambles of all ls or all US followed by a marker signal is well known, the details of preamble control 137 are not described. The later-described burst counter 163 of FIG. 7 could be used to writepreamble 10. This possibility will become apparent from the description of postamble 24 recording. Such sequencing is readily established by microprogramming.

Immediately after the marker signal of all 0s and all ls having been recorded, the first byte of data to be recorded is sent to write circuits 42 for recording. Before tape motion is initiated, OTC 33 effected transfer of the first byte of data from channel 30 to I/O register 48. Details of such transfer are known and not pertinent to an understanding of the present invention. One manner of obtaining and temporarily storing the first byte of data is the utilization of the start pulse on line 138 to transfer the byte of data to byte-storage register 160 (FIG. 6). This transfer is effected by AND-circuits 168 which receive the data signals from I/O register 48. (This latter connection is not illustrated in FIG. 2.) Therefore when a preamble is started by a start pulse, the first byte of data is made readily available within the control unit by transferring it to the byte storage register 160. Upon completing premable 10 by preamble control 137, an

16 end of preamble signal is supplied through OR-circuit 144 to actuate AND-circuits 147, thereby transferring the first data byte to write circuits 42. It may be noted that the start pulse on line 138 is not supplied until after the channel has supplied a SVC OUT signal indicating that the data byte is available.

The end of preamble signal also conditions the control unit to perform steps 64 through 71 of the write flow chart. This is accomplished by enabling AND-circuit 139 to pass a write clock pulse from line 136 to set steering latch 141. OR-circuit 140 will pass other signals during the write operations for setting steering latch 141 at the end of a write resync as well as during read operations.

Steering latch 141 gates the next SVC IN on line 38 through AND-circuit 142 to generate CHL SVC IN on line 38a. This signifies to channel 30 that control unit 32 is ready to receive the second byte of data. The first byte, of course, remains stored in byte storage register 160 until preamble 10 is written.

The tally of the number of data bytes that have been recorded is held in byte counter 143. The contents of byte counter 143 are altered in accordance with steps and 70. Since SVC IN indicates completion of one byte being recorded, the line 38 SVC IN signal is gated through AND-circuit 142 to byte counter 143. The AND-circuit 142 output is also supplied through OR-circuit 173 as the CHL SVC IN signal. AND-circuit 142 is enabled to pass the SVC IN signal only when latch 141 is set (i.e., during recording of data in a write operation).

The SVC IN signal is generated by known circuits. When OTC 33 determines write circuits 42 have recorded a data byte, it generates a SET SERVICE IN (SET SVC IN) pulse. This pulse is supplied over line 190 to set SVC IN latch 191. Latch 191 then supplies the SVC IN DC signal until reset by either a SVC OUT signal, CMD OUT signal, or a later-described PSEUDO SVC OUT (P SVC OUT) signal.

Step 68 is performed in the write resync circuits of FIG. 7. During a write operation, the CMD OUT signal sets WRITE STOP latch 151. CMD OUT together with the line WRITE signal enables AND-circuit to pass the next occurring SVC IN signal for setting WRITE STOP latch 151. Such usage of SVC IN ensures that the meaning of the CMD OUT signal is stop. Remember, as described before, CMD OUT may have several meanings depending upon the inbound signal at that moment. Stop is defined as CMD OUT in answer to SVC IN (i.e., CMD OUT is received after a function is being performed by control unit 32). Reset line 152 indicates that, during initialize, WRITE STOP latch 151 is reset to the inactive condition. When CMD OUT signal is not received, no action is taken.

Then, TEST SVC OUT test step 69 is performed. SVC IN again samples steering AND-circuit 142 (FIG. 6) to generate CHL SVC IN signal, which alters byte counter 143 by unity and gates out one byte of data from l/O register 41 to write circuits 42. It also notifies channel 30 to supply another data byte for recording.

Completion of writing one set of data signals is determinated by 13:0 detector 155 (FIG. 6) indicating that byte counter 143 contains zero (B O). If 13:0 is not supplied, the just-described write cycle is repeated. As later described, if 13:0, the write resync circuits of FIG. 7 are activated to reset steering latch 141 for terminating the write operation (one set of data signals has been recorded). This action is accomplished when SVC OUT is received over line 37 and B:0. AND-circuit 157 is jointly responsive to these signals and a write signal on line 135 to set END OF DATA latch 158. When set, latch 158 activates the FIG. 7 write resync circuits by setting write resync latch 161. To reset latch 158, AND-circuit 169 jointly responds to write signal on line 135 and the SET SVC IN signal on line 190.

A resync burst, longitudinal check digit and the marker signals are written only after the first byte of data for the next data set to be recorded has been received. Such byte of data is indicated as being available by SVC OUT. SVC OUT is not available during the writing of the check digit, marker signals, and resync signals B. Since no additional SVC OUT is received, a PSEUDO SVC OUT (P SVC OUT) signal is generated to step the later-described write resync recordings. When data signals are being recorded, the SET SVC IN and SVC OUT signals step operations. During resync recording, SVC IN is gated by AND-CIR- cuit 195 (FIG. 6) through delay 196 to generate P SVC OUT. AND-circuit 195 is enabled whenever steering latch 141 is reset (data is not being recorded) to simulate responses from channel 30.

The number of resync signals B that have been recorded plus recording to marker signals is tallied in burst counter 163 (FIG. 7). Counter 163 is stepped once each time AND-circuit 162 passes SET SVC IN. Circuit 162 is enabled by write resync latch 161 being set and writing not being terminated, as indicated by a signal on line 213. This signal is described later with respect to stop write sequencing. Counter 163 supplies its signal state indications to burst count decoder 164, which translates all signal states of the counter into one of 35 signal conditions. When burst counter 163 contains unity, step 74 of FIG. 3 is performed. An activating signal is supplied over line 167 (FIGS. 7 and 2) to OTC 33 for gating a check digit over cable 197 to write circuits 42. The generation of such check digits is well known and is not further described for that reason. Steering latch 141 is now reset by AND-circuit 192 supplying a signal over line 166 to AND-circuit 159. The write clock pulse on line 136 is passed by AND-circuit 159 to reset latch 141. AND- circuit 192 only supplies this resetting signal when stop write latch 151 is reset (i.e. not a stop sequence).

At this point, there is a deviation in operation steps between FIGS. 3 and 7. In the FIG. 3 embodiment, step 74 is executed before receipt of SVC OUT. In FIG. 7, SVC OUT is received before a check digit is sent to write circuits 42. Either embodiment is satisfactory. FIG. 7 could be modified to gate the check digit upon B without waitnig for SVC OUT.

The next step is to record marker signal 13. In FIG. 7, marker signal 13 is written during the two steps to write the marker signal of all ls and all 0s and occurs as burst counter 163 steps through counts 2 and 3. At count 2, a write all ls signal is supplied by decoder 164 through OR-circuit 170 to write circuits 42. When burst counter 163 has a count of 3, a write all Os signal is supplied through OR-circuit 171 to write circuits 42. Write all Us or all ls indicates the appropriate signal is simultaneously recorded in all tracks. This action completes the writing of the marker signal as set forth in step 77 of FIG. 3.

In burst counter steps 4 through 31, a burst of ls is recorded. Accordingly, when decoder 164 senses that the tally is equal to 4 (K=4), write-all-ls latch 172 is set. It supplies a write-all-ls signal through OR-circuit 170 to Write circuits 42. A 1 is written in each and every track during each cycle of the control unit as burst counter 163 proceeds through its count. When counter 163 has reached 32, write-all-ls latch is reset, thereby removing the writeall-ls signal. Also, during burst counter steps 32 and 33, marker signal is recorded by the all-Os and all-ls signals being supplied in that order to write circuits 42. Write resync latch 161 is reset by decoder 164, K=34 signal, thereby terminating the writing of the resynchronization burst of signals. To restart recording of data signals in data set 16, line 175 signal (K=34) simultaneously enables AND-circuit 176 to pass a write clock pulse to set steering latch 141 (FIG. 6), resets write resync latch 161 and gates the first data byte in register 160 (FIG. 6) to write circuits 42. The latter is accomplished by K=34 passing from line 175 through OR-circuit 144 to enable AND-circuits 147 of FIG. 6. Write resync latch 161 being reset terminates resync signal recording. Steering latch 141, upon being set, automatically sequences writing the next set of data signals in the same manner as heretofore described.

The above-described operations for writing sets of alternate data signals D and resynchronization bursts B are repeated until the last byte of data has been recorded. This is signified by channel 30 supplying a CMD OUT signal. The CMD OUT signal sets write stop latch 151 of FIG. 7 to initiate sequences for terminating the writing operation. The write signal on line and SVC in signal on line 38 jointly enable AND-circuit 150 to pass CMD OUT to set write stop latch 151. Referring now to FIG. 1, it is seen that the last byte of data may occur at any time during the recording of a set of data signals having a maximum length of 1,024 bytes. Therefore, to ensure that the truncated block of data bears the previously described integral multiple relationship to the number of ROC states, it may be necessary to write padding signals P in subset 22b. A write termination operation is then initiated which includes writing postamble 24. If CMD OUT is received at the completion of recording a set of data signals, a marker signal and postamble 24, are written. Pad l detector 216 is connected to the lower order four bit positions or stages of byte counter 143. Therefore, detector 216 detects a byte count within the modulus of ROC 44 to ensure a recording length having an integral multiple number of signals of the ROC 44 modulus.

When CMD OUT is received in a middle of a data set, marker signal 23 is first written followed by a burst of 0 signals represented in FIG. 1 by the padding signals P. In reading in the forward direction, marker signal 23, which is an all-ls byte followed by an all-Os byte, signifies the end of data. Reading in the reverse direction, the postamble (i.e.. all-ls), followed by a 0 signal indicates that data set 22 is being read. However, the all-Os bytes indicate no data is to be transferred out of the control unit. However, the byte counter 143 may be tallied such that the count is proper when marker signal 21 is to be read. Data is transferred upon the detection of marker signal 23. Therefore, the write STOP sequence must record an all-ls byte followed by a sufficient number of all-Os bytes to make the length of the data set bear the integral multiple relation to the number of ROC states and then record an all-ls postamble. The above discussion assumes that the check digit associated with the subset 22a of that data signal has been written.

Returning now to FIGS. 6 and 7, the STOP signal from latch 151 is supplied over line 200 to delay write terminate circuit 201 (FIG. 7). Circuit 201 enables the termination of write operations to be delayed until after the padding signals and preamble 24 have been recorded. STOP is also supplied to AND-circuit 202 which is jointly responsive to STOP and to write resync latch 161 being reset to supply a stop ends count signal to burst counter 163. The significance of this action is that AND-circuit 202 detects the CMD OUT being received during the recording of data; that is, write resync latch 161 is reset. It is desired to immediately record a check digit. This is accomplished by setting burst counter 163 to unity for supplying a gateenabled check digit signal over line 167 to OTC 33. This gating is accomplished by the next-occurring write clock signal. Immediately after recording the last data signal, STOP is also supplied through OR-circuit 204 to enable AND-circuit 162 for incrementing burst counter 163 each time a SET SVC IN signal is received over line 190. Circuit 201 supplies a NOT TERMINATE signal over line 213 to enable AND-circuit 162. AND-circuit 192, which is jointly responsive to K=1 and NOT STOP cannot now reset steering latch 141. Rather, as soon as write stop latch 151 is set its signal on line 200 is supplied through OR- circuit 205 (FIG. 6) to immediately reset steering latch 141. Note that this resetting does not have to wait for a write clock pulse to be emitted by OTC 33. Upon receipt of the next SET SVC IN signal on line 190, SVC IN latch 191 is set. Again AND-circuit 195 is responsive to steering

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5109385 *Apr 27, 1989Apr 28, 1992International Business Machines CorporationEnhanced data formats and machine operations for enabling error correction
US5172381 *Apr 26, 1991Dec 15, 1992International Business Machines CorporationEnhanced data formats and machine operations for enabling error correction
US5363252 *Jun 30, 1993Nov 8, 1994International Business Machines CorporationMethod and system for track skew tolerant acquistion burst sequence validation in a data storage system
EP0395205A2 *Mar 8, 1990Oct 31, 1990International Business Machines CorporationEnhanced error recovery track recording
U.S. Classification360/50
International ClassificationG11B20/20
Cooperative ClassificationG11B20/20
European ClassificationG11B20/20