|Publication number||USRE28997 E|
|Application number||US 05/623,863|
|Publication date||Oct 5, 1976|
|Filing date||Oct 20, 1975|
|Priority date||Aug 30, 1973|
|Also published as||US3845399|
|Publication number||05623863, 623863, US RE28997 E, US RE28997E, US-E-RE28997, USRE28997 E, USRE28997E|
|Inventors||Carlos D. Cardon, Lawrence P. Griffone|
|Original Assignee||Sperry Rand Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (3), Classifications (9)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Prior art detectors of an analog signal of a selected frequency and amplitude have been designed using an analog filter that passes only an analog signal of the selected frequency and amplitude followed by a full-wave or half-wave rectifier and then a Schmitt trigger. Because of the availability of inexpensive and reliable digital circuits it is desirable that previous analog techniques be replaced by digital techniques as proposed by the present invention.
In the digital filter of the present invention.Iadd., .Iaddend.an analog input signal of a frequency FA is initially tested for minimum amplitude and then converted to a binary digital waveform which is edge detected to provide an output pulse for every cycle of the analog input signal. The first output pulse sets a sample time generator and the pulses are counted over the sample time TS. If the pulse count is within the bandpass at any time during the sample time TS the counter and a binary decoder set a flip-flop to a True state. This flip-flop is sampled at the end of the sample time and the True output is transferred to a storage element which is switched to the True condition. The True condition of the storage element after a one pulse width delay time then resets the counter back to O. A time generator synchronizer driven by the output of the edge detector is disabled if the condition of the storage element is True. During the next successive sample time TS the procedurre is repeated with the counter counting the number of pulses from the edge detector. If the number of pulses counted is within the bandpass the binary decoder continues coupling a True condition to the storage element with the counter reset as before and the time generator synchronizer being disabled. If during the next sample time TS the counter counts a number of pulses without the bandpass the binary decoder couples a False output signal indicating that the analog input signal is of a frequency outside the bandpass. This False condition signal is delayed one pulse width to activate the time generator synchronizer in preparation for the next incoming pulse from the edge detector which incoming pulse initiates the sample time generator after which the detector-comparing operation is repeated.
FIG. 1 is a block diagram of the special-purpose digital filter of the present invention.
FIG. 2, consisting of FIGS. 2a, 2b, is a logic level drawing of the special-purpose digital filter of FIG. 1.
FIG. 3 is a timing diagram illustrating the operation of the special-purpose digital filter of FIG. 1.
With particular reference to FIG. 1 there is presented a block diagram of the special-purpose digital filter of the present invention, the elements thereof being illustrated in detail at their logic level in FIGS. 2a and 2b. The special-purpose digital filter of the present invention basically establishes a fixed sample time TS during which the actual number NA of cycles or pulses of a sampled signal are counted. The number NA is then compared to the minimum number NL and the maximum number NH of cycles or pulses that define the bandpass width of the filter. If within that range, i.e., .[.NL ≦ NA ≦ NH .]. .Iadd.NL ≦ NA < NH .Iaddend. a first True signal is generated and if without the range, i.e., .[.NL > NA > NH .]. .Iadd.NL > NA ≧ NH, .Iaddend.a second False signal is generated. The True and/or False signals are then set into a flip-flop and the flip-flop output is in turn clocked into the output storage element (flip-flop) at the end of the sample period. Thus the True condition of the output storage element indicates that a signal meeting the amplitude and frequency condition is present at the input to the circuit. Conversely, the False condition indicates that the signal does not meet these conditions. Using the timing diagram of FIG. 3 to explain the operation of the present invention illustrated in FIGS. 1, 2a, 2b certain parameters shall be assumed by way of example to better illustrate the operation of the present invention in its preferred embodiments of FIGS. 2a, 2b:
FL = 900 Hz
FH = 3000 Hz
TS = 1/1.5 × .[.10- 2 .]. .Iadd.10+ 2 .Iaddend. Hz = 6.67 × 10- 3 sec.
Thus the sampled signal shall be sampled over a duration of 6.67 × 10- 3 sec. and if the sampled signal frequency FA is within the bandpass width, i.e., .[.NL ≦ NA ≦ NH .]. .Iadd.NL = NA < NH, .Iaddend.the filter shall .[.generated.]. .Iadd.generate .Iaddend.a True signal output and, alternatively, if the sample signal frequency is without the bandpass width the filter shall generate a False signal output.
Referring to the signal waveforms of FIG. 3, the analog signal A of a frequency FA is coupled to comparator 10. Signal A is initially coupled to amplifier 10-1 which is an isolation and threshold detector which compares signal A to a threshold level and if signal A is above the threshold level couples signal A to converter 10-2. Converter 10-2 converts the analog signal A of a frequency FA to the digital signal B. The digital signal B is then coupled to edge detector 20 which produces, as an output, signal C which consists of a single short duration output pulse for every complete input cycle of signal B. Signal C is, in turn, coupled in parallel to counter 30 and sample time controller 40. At binary counter 30-1 the pulses of signal C, beginning at time t0, are counted with the running total count being decoded by binary decoder 30-2 which, in turn couples a decoder True signal to lower band edge detector 30-3 .[.if.]. .Iadd.when .Iaddend.the decoded binary count is equal to the lower bandpass.Iadd., i.e., when NA = NL, .Iaddend.and a decoder False signal to upper band edge detector 30-4 .[.if.]. .Iadd.when .Iaddend.the decoded binary count is .[.above.]. .Iadd.equal to .Iaddend.the upper bandpass.Iadd., i.e., when NA = NH. .Iaddend.At sample time controller 40 the first pulse of signal C triggers time generator synchronizer 40-1 coupling a single short duration pulse to synchronizer edge detector 40-2 that couples the signal D to the sample time generator 60. Signal D triggers time base generator 60-1 to generate signal E which is, in turn, coupled to time base leading edge detector 60-2 which generates as an output therefrom signal F which is coupled to edge triggered bistable multivibrator or flip-flop 80-1 of memory element 80 by way of inverter 80-2 and to time base trailing edge detector 70-1 which generates an output signal G. Signal G resets the binary counter 30-1 to O and through NAND gate 70-3 and inverter 70-4 sets bistable multivibrator or flip-flop 70-2. At this time, edge triggered bistable multivibrator 80-1 of memory element 80 is coupling a relatively low level False state of output signal O to an output line 80-3 and as a first input to NAND gate 50-1 of synchronizer controller 50.
Counter 30 is set to a bandpass of a count of 6 - 20, .Iadd.i.e., 6 ≦NA < 20, .Iaddend.and, accordingly, at the count of 6 binary decoder 30-2 couples a True decode pulse to lower band edge detector 30-3 which, in turn couples decode True signal H to bistable multivibrator 70-2 causing it to change its state. Binary counter 30-1 continues counting the subsequent pulses 7 - 19 of signal C causing lower band edge detector 30-2 to remain in its previously set True state.
At the end of the sample time TS time base generator 60-1 couples the second pulse of signal E to time base leading edge detector 60-2 which, in turn, couples the second pulse of signal F to edge triggered bistable multivibrator 80-1 by way of inverter 80-2 which gates the state of bistable multivibrator 80-2 therein causing memory element 80 to couple to its output line the relatively high level True state of output signal O and through NAND gate 70-3 and inverter 70-4 causes bistable multivibrator 70-2 to change to a False state. The concurrent application of the signal G and signal O at NAND gate 50-1 disables the time generator synchronizer 40-1.
Under the above described conditions the input signal A has been assumed to be within the bandpass of a pulse count of 6 - 20, .Iadd.i.e., 6 ≦ NA < 20, .Iaddend.e.g., FL = 900 Hz, FH = 3000 Hz at a sample time TS of 6.67 × 10- 3 sec. If the count had been .Iadd.equal to or .Iaddend.greater than 20.Iadd., i.e., NA ≧ 20, .Iaddend.at time t1, e.g., after sample time TS binary decoder 30-2 would have coupled the appropriate signal to upper band edge detector 30-4 which, in turn, would have coupled a decode False pulse to NAND gate 70-3 and inverter 70-4 which, in turn, would have changed the state of bistable multivibrator 70-2 which False state of bistable multivibrator 70-2 would have caused edge triggered bistable multivibrator 80-1 to couple the low level False state of output signal O to output line 80-3 when gated by inverter 80-2. Alternatively, if the count had been less than 6.Iadd., i.e., 6 > NA, .Iaddend.at time t1, e.g., after sample time TS, binary decoder 30-2 would not have coupled any True decode signal to lower band edge detector 30-3 whereby no high level pulse of signal H would have been coupled to bistable multivibrator 70-2 causing edge triggered bistable multivibrator 80-1 to continue coupling the relatively low level False state of output signal O to output line 80-3 of memory 80 when triggered by inverter 80-2. With the output signal A continuing to be of a frequency FA within the bandpass, memory element .[.A.]. .Iadd.80 .Iaddend.continues coupling its relatively high level True state of output signal O to its output line 80-3. However, as at the end of the sample time TS at time t1 the second pulse of signal F from time base trailing edge detector 70-1 has reset binary counter 30-1 to O the above described sequence repeats itself testing the incoming signal A for its frequency FA to determine, if at any time, it is within or without the bandpass and to provide a corresponding high level True state or low level False state of output signal O on its output line 80-3.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
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|U.S. Classification||327/45, 327/552, 327/49|
|International Classification||H03D3/04, H03D3/18|
|Cooperative Classification||H03D3/04, H03D3/18|
|European Classification||H03D3/18, H03D3/04|