|Publication number||USRE29885 E|
|Application number||US 05/717,706|
|Publication date||Jan 16, 1979|
|Filing date||Aug 25, 1976|
|Priority date||Apr 5, 1972|
|Publication number||05717706, 717706, US RE29885 E, US RE29885E, US-E-RE29885, USRE29885 E, USRE29885E|
|Inventors||Wolfgang F. W. Dietz|
|Original Assignee||Rca Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Non-Patent Citations (1), Referenced by (1), Classifications (12), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
BACKGROUND OF THE INVENTION
This invention relates to a boosted B+ voltage regulator for a deflection circuit of a television receiver.
It is desirable to regulate the operating supply voltage of the horizontal deflection circuit of a television receiver in order to supply constant energy to the horizontal deflection winding from one deflection cycle to another. Variations in the supply voltage change the amount of scanning current in the deflection winding and result in undesirable picture width variations. Additionally, it is customary to derive the ultor voltage for the picture tube from the horizontal deflection circuit by rectifying the flyback pulses produced in the horizontal output transformer during the retrace interval of each deflection interval. A variation of the supply voltage will vary the flyback pulse energy and hence the ultor voltage, resulting in picture brightness variations and a further variation in picture width. Furthermore, operating voltages for other portions of the receiver, such as the video or audio stages, may also be derived from the horizontal deflection circuit, and it is desirable that these voltages also be regulated. Of course, it is known that separate voltage regulators may be utilized for the deflection and other circuits, but such an approach is costly and increases the complexity of the receiver. Furthermore, in the interest of economy, it is desirable to rectify the alternating current line voltage directly without using a power transformer to step up the line voltage to supply a high enough level of operating voltage for the deflection circuit. The present invention is directed to a circuit which boosts and regulates the rectified alternating current voltage for application to a television receiver deflection circuit.
In accordance with one embodiment of the invention, a boosted B+ circuit for a deflection system includes a source of direct current voltage subject to undesirable voltage variations. Switching means in the deflection system operable during each deflection interval are coupled through an inductance means to the voltage source for receiving operating current therefrom. A winding of the inductance provides a source of alternating current as the switching means operates from the one state to another during each deflection cycle. Active current conducting means are coupled to the winding and a terminal of the voltage source for rectifying the alternating current voltage and adding it to the direct current voltage. In an embodiment in which the boost voltage is regulated, control means are coupled to the active current conducting means for determining its period of conduction during each deflection cycle. Voltage sensing means are coupled to the control means and to a source of voltage representative of variations of the direction current voltage for providing a signal for the control means for determining the period of conduction of the active current conducting means and hence the amount of energy added to the direct current voltage source to keep it substantially constant.
A more detailed description of a preferred embodiment of the invention is given in the following description and accompanying drawing of which:
FIG. 1 is a schematic diagram, partially in block diagram form, of a deflection system embodying the invention;
FIG. 2 is a graph plotting the direct current voltage at two points in the circuit of FIG. 1 against line voltage;
FIG. 3A-3G are normalized waveforms obtained at various points in the diagram of FIG. 1; and
FIG. 4 is a schematic diagram of another embodiment of a regulator circuit according to the invention.
FIG. 1 is a schematic diagram, partially in block form, of a deflection system 10 embodying the invention. With the exception of the regulator circuit, to be described subsequently, the horizontal deflection circuit is of the retrace driven type similar to that disclosed in U.S. Pat. No. 3,452,244. This circuit includes a commutating switch 11, comprising a silicon controlled rectifier (SCR) 12 and an oppositely poled damper diode 13 coupled between a winding 27a of an input choke 27 and ground. For purposes of explanation of the deflection circuit the other terminal of winding 27a may be considered to be connected to a source of positive direct current voltage. Commutating switch 11 is coupled through a commutating coil 22 and a capacitor 23 to a trace switch 14. Trace switch 14 comprises an SCR 15 and an oppositely poled damper diode 16. A capacitor 24 is coupled between the junction of coil 22 and capacitor 23 and ground. Trace switch 14 is coupled through the series combination of a horizontal deflection winding 17 and an S-shaping capacitor 18 to ground, and through a primary winding 19a of a horizontal output transformer 19 and a DC blocking capacitor 20 to ground.
A secondary, or high voltage, winding 19b of transformer 19 produces relatively large amplitude flyback pulses during the retrace interval of each deflection cycle. These pulses are applied to a high voltage multiplier and rectifier circuit 21 for producing a direct current high voltage in the order of 27 kilovolts for use as the ultor voltage of a television picture tube (not shown).
A horizontal oscillator 25 is coupled to the gate electrode of commutating SCR 12 and produces a pulse during each deflection cycle slightly before the end of the trace interval to turn on SCR 12 to initiate the commutating interval. A waveshaping network 26 is coupled between a tap on the input choke winding 27a and the gate electrode of trace SCR 15 to form a signal to enable SCR 15 for conduction during the second half of the trace interval.
In the regulator portion of the deflection system, a source of alternating current line voltage is rectified by a rectifying diode 28 and filtered by a filtering network 29. The direction current voltage obtained from the filtering network 29 is coupled through a diode 30 and a current limiting resistor 31 to one terminal of a storage capacitor 32, the other terminal of which is grounded. The junction of resistor 31 and capacitor 32 is coupled to one terminal of winding 27a of input choke 27 for supplying the direction current operating potential to the deflection circuit.
A winding 27b of input inductance 27 has one terminal thereof coupled through an inductance 33 to the anode of a voltage regulating SCR 34. The cathode of SCR 34 is coupled to capacitor 32. The junction of winding 27b and inductance 33 is coupled through a capacitor 38, a resistor 37, a resistor 39 and a resistor 40 to the base electrode of a control transistor 35. The emitter electrode of transistor 35 is coupled to the gate electrode of SCR 34, and its collector electrode is coupled through resistor 36 to the junction of resistors 37 and 39. A clipping zener diode 43 has its cathode coupled to the junction of resistors 37 and 39 and its anode coupled to one terminal of capacitor 32. An integrating capacitor 42 is coupled between the junction of resistors 39 and 40 and capacitor 32.
A voltage divider network comprising series coupled resistors 44 and 45 and potentiometer 46 is coupled across capacitor 32. A zener diode 47 has its anode coupled to the junction of resistors 44 and 45 and its cathode coupled to the base electrode of transistor 35.
At the beginning of the trace interval the deflection current in deflection winding 17 is at a maximum negative amplitude and is linearly decreasing as current is conducted through diode 16 and winding 17 to charge capacitor 18. About the middle of the trace interval the deflection current goes through zero and reverses; damper diode 16 is not cutoff and SCR 15, which had been enabled during the first half of trace by a positive gate pulse from waveshaping network 26, now conducts, providing a path to ground through winding 17 for energy stored in capacitor 18, which capacitor 18 also serves as an S-shaping capacitor. It should be noted that the average voltage across capacitor 18 is in the order of 50 volts and the capacitor is large enough such that during each deflection cycle it charges and discharges only partly about the nominal 50 volts average charge.
During the trace interval commutating switch 11 is open, and capacitors 23 and 24 are charged in parallel through commutating coil 22 by the energy stored in winding 27a of input choke 27. Slightly before the end of trace a positive gate from horizontal oscillator 25 enables SCR 12 and it starts to conduct, initiating the commutating interval. At this time first and second resonant circuits are formed; the first comprising SCR 12, coil 22 and capacitor 24, and the second comprising SCR 12, coil 22, capacitor 23 and SCR 15 which now conducts a current in two directions.
The resonant current through SCR 15 from capacitor 23 increases more rapidly than the increasing deflection current and when the former exceeds the latter SCR 15 is turned off. At this time the current switches to diode 16, but when the resonant current from capacitor 23 reverses, diode 16 is switched off, disconnecting the deflection current path, ending the trace interval and initiating the retrace interval. During the retrace interval, which is totally included within the commutating interval, energy is supplied through switch 11, coil 22 and capacitors 23 and 24 through the deflection winding 17 to replenish the charge on capacitor 18 and from switch 11, coil 22 and capacitors 23 and 24 to replenish the energy in the primary winding 19a of horizontal output transformer 19.
During the energy exchange retrace interval SCR 12 and diode 13 are rendered nonconducting as the resonating voltage in turn reverse biases each device, opening switch 11. Also, as the resonating current decreases the reverse bias across diode 16, it again conducts, initiating the next trace interval.
The commutating interval ends shortly after the beginning of the trace interval as the currents in capacitors 23 and 24 approach zero and diode 13, which has been conducting for a second time during the commutating interval, is cutoff. During the commutating interval when switch 11 was closed winding 27a was placed between the source of operating potential and ground and hence conducted a linearly increasing current. At the end of the commutating interval, when switch 11 opens, the energy stored in winding 27a again charges capacitors 23 and 24 in preparation for the next commutating interval.
From the above description of operation of the deflection circuit it should be understood that any variation in the direct current operating potential coupled through winding 27a to the commutating portion of the circuit will vary the amount of energy restored to the primary winding 19a and capacitor 18 and hence cause undesirable variations in ultor voltage and picture width.
FIG. 2 is a graph plotting the relationship of alternating current line voltage (abscissa) to the direct current operating potential (ordinate) produced by the power supply and regulator portion of the deflection system of FIG. 1. The curve 48 illustrates the DC output potential of rectifier 28 and filtering network 29 as a function of line voltage. As the line voltage varies from 105 to 135 volts the DC voltage varies from about 130 to 170 volts. As these line voltage variations about a nominal 120 volts may occur frequently, it is obvious that some regulation scheme is essential. Furthermore, it is desirable to operate the deflection circuit at a constant DC voltage of about 170 volts as illustrated by curve 49 of FIG. 2, which is above the potential available from the rectified line voltage except at extremely high line voltage. The function of the regulator portion of the deflection system of FIG. 1 is to boost the line-rectified voltage and to regulate it at the boosted point as the line voltage varies. To accomplish this the boost-regulator circuit adds to the rectified line voltage the voltage represented by the difference between the curves 48 and 49.
FIGS. 3A-3G illustrate normalized voltage and current waveforms obtained at various points of the circuit of FIG. 1 and will be referred to in the subsequent discussion of the regulator portion of the circuit. The time base and relative amplitudes of the waveforms are not drawn to scale to simplify the drawing. For convenience, the points of the circuit of FIG. 1 at which the waveforms of FIGS. 3A-3G are obtained are lettered A-G in the circuit.
During initial operation of the circuit, occurring when the television receiver is switched on, the line-rectified voltage is coupled through diode 30 and current limiting resistor 31 to input choke winding 27a to initiate operation of the deflection circuit as described above. As the deflection circuit operates a voltage waveform 50 of FIG. 3A is developed across the commutating switch 11. The commutating interval is represented by the 0 volt portion of waveform 50. This waveform is coupled by transformer action to winding 27b of input choke 27 and appears inverted as waveform 51 of FIG. 3B with reference to ground at the junction of winding 27b, capacitor 38 and inductance 33. In the embodiment of FIG. 1 it is the positive portion, or commutating interval portion, of waveform 51 which is rectified by SCR 34 to be added to the line-rectified voltage appearing across capacitor 32. In this arrangement energy is taken from the deflection circuit only during the commutating interval and hence has very little effect on the operation of the deflection circuit during the trace interval.
Waveform 51 is also coupled through capacitor 38 and resistor 37 to the cathode of zener diode 43, the anode of which is returned to the V0 supply. Zener diode 43 is selected to clip the positive portion of waveform 51 such that there is always a peak to peak voltage across it regardless of variations in the peak positive level of waveform 51. The fixed clipped waveform across zener diode 43 is illustrated by voltage waveform 52 of FIG. 3C. The waveform 52 is coupled through a resistor 36 to supply the collector electrode operating potential for control transistor 35. Waveform 52 is integrated by resistor 39 and capacitor 42 to form a constant peak to peak voltage sawtooth which is then coupled through a resistor 40 to bias the base electrode of transistor 35.
The voltage divider comprising series resistors 44, 45 and potentiometer 46 senses any variations in the V0 supply voltages. Zener diode 47 coupled between the base of transistor 35 and the junction of resistors 44 and 45 provides a variable conduction path altering the base drive current supplied to transistor 35 and hence the time that SCR 34 is turned on during each deflection cycle.
For a condition of low line voltage the V0 direct current voltage also tends to decrease to a less positive level. This results in less of a voltage drop across resistor 44. With less of a positive voltage at the anode of zener diode 47 the voltage at its cathode can rise a corresponding amount before the zener diode 43 conducts. Thus, the sawtooth voltage from capacitor 42 supplies only the base circuit of transistor 35 and all of the current from capacitor 42 drives the base of the current amplifier 35. The voltage at the emitter electrode of transistor 35 then in turn gates on SCR 34 at time T0 (the beginning of the commutation interval as indicated by the timing lines common to all of FIGS. 3A-3G) and enables SCR 34 to conduit until T2, occurring shortly after the end of the commutation interval. In this manner storage capacitor 32 is charged with a maximum amount of energy and hence increases the V0 potential. The sawtooth voltage waveform applied to the base electrode of transistor 35 during the low line voltage conditions is illustrated by waveform 53 of FIG. 3D. The current waveform of the main conduction path of SCR 34 during this condition is illustrated by waveform 55 of FIG. 3F.
Conversely, during a condition of high line volage, the V0 supply voltage tends to become more positive and there is an increased voltage drop across the voltage divider and resistor 44. This raises the cathode and anode potential of zener diode 47. Zener diode 47 then starts to conduct earlier in time along the time base of the sawtooth voltage across capacitor 42 and thereby provides a bleed path, through resistor 45 and potentiometer 46, for current from capacitor 42 which would otherwise supply the base electrode of transistor 35. The sawtooth voltage must then rise to a more positive level before transistor 35, and consequently, SCR 34, conduct. This shortens the period within the commutating interval during which energy is added to capacitor 32 and hence lowers the V0 voltage.
Resistor 45 and potentiometer 46 are in the discharge path for capacitor 42 once zener diode 47 conducts and hence determine the rate of removal of the sawtooth bias for transistors 35. Potentiometer 46 is adjusted to set the voltage at which regulation starts.
Under the condition of extremely high line voltage with SCR 34 is not turned on at all, the deflection system operating current will be conducted through diode 30. In this situation current limiting resistor 31 prevents a large increase in voltage as the current is switched from SCR 34 to diode 30.
Inductance 33 in series with SCR 34 is selected to control the rate of current rise and hence shuts off SCR 34 at T2 after the end of the commutation interval. The size of inductance 33 may be selected to control the maximum amount of energy passed by SCR 34 and stored in capacitor 32. Energy from inductance 33 and the leakage inductance of choke 27 passed on to capacitor 32 can be seen as the positive excursion of waveform 50 of FIG. 3A during the interval T1 - T2.
Since the V0 supply is regulated as it is applied to input choke 27, auxiliary power supply circuits coupled to auxiliary windings of the choke 27, or to windings of the horizontal output transformer 19, such as a rectifying circuit for supplying operating voltage to the television receiver video circuits or a supply for energizing the filaments of the picture tube, will also be regulated.
FIG. 4 is a schematic diagram of another embodiment of a boosted B+ regulator for a deflection system according to the invention. Those circuit elements in FIG. 4 which perform similar functions to the correspondingly numbered elements in FIG. 1 have the same reference numerals as in FIG. 1. For convenience, the actual deflection circuit has been omitted from FIG. 4. However, it is to be understood that a deflection circuit similar to that shown in FIG. 1 may be utilized with the embodiment shown in FIG. 4. The boosted B+ regulator circuit of FIG. 1 utilized an SCR 34 as a half-wave rectifier for an alternating current wave derived from the input choke 27. In addition to the regulation aspect the FIG. 1 circuit provided a B boost such that the operating potential V0 supplied to the deflection circuit was in the order of 170 volts. In the FIG. 4 embodiment a full-wave rectifier arrangement is utilized to provide an even greater regulated potential, the boosted operating potential being in the order of 200 volts. Generally, with the exception of the full-wave rectifier circuit portion, the operation of the regulator circuit is similar to that of FIG. 1.
In FIG. 4 a source of alternating current line voltage is rectified by a rectifying diode 28 and filtered by a filtering network 29. During initial operation of the receiver and under extremely high line voltage conditions the operating potential for the deflection circuit is supplied through the series arrangement of a diode 30, a current limiting resistor 31, and through a winding 27a of the input choke 27 to the commutating switch 11 of FIG. 1.
During a low line voltage condition the operating potential V0 ' tends to decrease. During the commutation interval of each deflection cycle the positive portion of waveform 51 is coupled through a winding 19c of the horizontal output transformer of FIG. 1, inductance 33 and rectified by SCR 34. The current through SCR 34 charges capacitor 32. This produces a higher voltage across the storage capacitor 32 which is coupled through winding 27a to supply the deflection circuit.
Similar to the arrangement of FIG. 1, during a low line voltage condition less voltage appears across the voltage divider network comprising resistors 44, 45 and potentiometer 46 and hence there is less voltage developed across resistor 44. This lowers the positive potential appearing at the anode of zener diode 47 and hence allows the base electrode potential of transistor 35 to rise to a higher voltage before zener diode 47 conducts. This allows transistor 35 to conduct during the entire commutation interval as the integrated sawtooth wave is coupled to the base electrode of transistor 35. Thus, transistor 35 gates on SCR 34 at the start of the commutation interval and SCR 34 passes current to charge capacitor 32 during the entire commutation interval, and slightly beyond to time T2, thereby providing a maximum voltage boost to the line rectified voltage.
In this embodiment a winding 19c of the horizontal output transformer of FIG. 1 has been added in series with the winding 27b of the input choke. Although the circuit may be operated without the addition of winding 19c the inclusion of this winding provides a flyback pulse which occurs within the commutation interval, the energy of which is simply added to the energy of the commutation pulse which is passed by SCR 34. This arrangement increases the energy which may be stored in capacitor 32 during the commutation interval.
Diode 60, having its cathode coupled to capacitor 61 and inductance 33 and its anode coupled to winding 27b, is oppositely poled to SCR 34 and enables rectification of the waveform 51 during the trace interval to further add to the boosted potential V0 '. During the trace interval when the trace portion of waveform 51 is negative, current is conducted by diode 60 and is stored in capacitor 61. This arrangement is analogous to the operation of a voltage doubler circuit, in which capacitor 61 is discharged during the next commutation interval, thereby adding its charge, which is essentially a control for each cycle, to the charge on capacitor 32. This charge is added during the condition of high line voltage as well as the condition of low line voltage as long as SCR 34 conducts.
Under conditions of high line voltage the voltage drops across the voltage divider and hence resistor 44 is greater, putting higher positive potential at the anode of zener diode 47. Thus, as in the FIG. 1 embodiment, zener diode 47 will conduct earlier in time during the period of the sawtooth voltage ramp applied to the base electrode of transistor 35. As zener diode 47 conducts it bleeds the base drive current from transistor 35 which then does not conduct until a later time in the period of the sawtooth ramp. Hence, SCR 34 is gated on for only a small portion, if any, of the commutation interval and less current is passed by it to charge capacitor 32 thereby tending to lower the output voltage V0 '. As mentioned above, diode 60 will still conduct during the trace portion of waveform 51, the regulation of the voltage being accomplished by SCR 34 and its associated control circuit.
In FIG. 4, a network 65 provides sensing of the commutation switch 11 waveform 50 of FIG. 3A to add a beam current regulation function to the circuit. The waveform 50 obtained from the anode of SCR 12 of switch 11 of FIG. 1 is rectified by a diode 62, filtered by a capacitor 63 and coupled through a resistor 64 to the junction of resistors 44 and 45 in the voltage divider. A higher beam current will result in a lower peak voltage of waveform 50 and hence lower the potential at the junction of resistors 44 and 45, thereby causing the regulator circuit to compensate and increase the amount of boost voltage as described above. As the sensing voltages for line voltage variations and beam current variations are in opposition to each other, the values of resistors 44 and 64 are selected to proportion the types of regulation. The beam regulation circuit may be used as will with the half-wave regulator circuit described in conjunction with FIG. 1.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3517253 *||May 22, 1968||Jun 23, 1970||Rca Corp||Voltage regulator|
|US3626238 *||Aug 25, 1969||Dec 7, 1971||Rca Corp||Thyristor controlled power supply circuits and deflection circuitry associated with a kinescope|
|US3641267 *||Jul 29, 1969||Feb 8, 1972||Ates Componenti Elettron||Stabilized voltage-step-down circuit arrangement|
|US3726999 *||Oct 20, 1971||Apr 10, 1973||Warwick Electronics Inc||Television receiver circuit providing feedback from horizontal driver transformer to power supply|
|US3737572 *||Jul 23, 1971||Jun 5, 1973||Zenith Radio Corp||Series-connected power supply and deflection circuits utilizing a single shunt regulator|
|US3949270 *||Jan 28, 1971||Apr 6, 1976||Hitachi, Ltd.||High voltage regulating circuit|
|US3970780 *||Sep 28, 1973||Jul 20, 1976||Sharp Kabushiki Kaisha||Constant-voltage power supply|
|1||*||Bissinger, Norbert, Stabilized Power Supply for the Horizontal Output Stage, German Publication Funkschau, 1970, No. 11, pp. 363-366.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5013980 *||Nov 1, 1988||May 7, 1991||Thomson Consumer Electronics, Inc.||Voltage regulator in a television apparatus|
|U.S. Classification||315/408, 348/377, 315/411, 348/730|
|International Classification||H04N3/185, H03K4/83|
|Cooperative Classification||H04N3/1856, H03K4/83, H04N3/185|
|European Classification||H04N3/185, H03K4/83, H04N3/185S|
|Apr 14, 1988||AS||Assignment|
Owner name: RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, P
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:RCA CORPORATION, A CORP. OF DE;REEL/FRAME:004993/0131
Effective date: 19871208