|Publication number||USRE30087 E|
|Application number||US 05/642,032|
|Publication date||Aug 28, 1979|
|Filing date||Dec 18, 1975|
|Priority date||Oct 20, 1972|
|Publication number||05642032, 642032, US RE30087 E, US RE30087E, US-E-RE30087, USRE30087 E, USRE30087E|
|Inventors||Marvin H. White, David H. McCann, Jr., Ingham A. G. Mack, Franklyn C. Blaha|
|Original Assignee||Westinghouse Electric Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Non-Patent Citations (4), Referenced by (8), Classifications (16), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates to charge coupled device (CCD) technology, and more particularly, to semiconductor apparatus for providing respective output signals indicative of the sequential transfer of minority carrier packets from a CCD shift register.
2. Description of the Prior Art
A new class of monolithic semiconductor apparatus adapted for storing and sequentially transferring electronic signals representing information in the form of packets of excess minority carriers localized in artificially induced potential wells has been disclosed by W. S. Boyle and G. S. Smith, in an article entitled "Charge Coupled Semiconductor Devices," B.S.T.J. April, 1970, pages 587-593, inclusive. Such apparatus comprises a metal-insulator-semiconductor (MIS) structure wherein a plurality of metal electrodes are disposed in a row over the insulator (dielectric) which in turn overlies and is contiguous with the surface of a semiconductor body. Sequential application of voltages to the metal electrodes induces potential wells adjacent the surface of the semiconductor body in which packets of excess minority carriers can be stored and between which these packets can be transferred. To insure predictable directionality of charge packet transfer, the transfer potential well must be asymmetrical at least during the transfer operation. As disclosed in the Boyle-Smith disclosure, at least three phase clock pulses are required to provide the requisite asymmetry for a uniform dielectric thickness under the gate electrodes and a homogeneous semiconductor.
A two-phase clock CCD system is disclosed in U.S. Pat. No. 3,651,349 issued to Dawon Kahng and Edward H. Nicollian. Charge transfer is accomplished in this configuration by the use of overlapping gate electrodes and/or non-uniform dielectric thicknesses under the gate electrodes so that an appropriately asymmetrical potential well is always formed whenever a voltage is applied to any gate electrode.
Charge coupled devices have also been noted to be particularly adapted to the fabrication of an imaging array where for example a parallel readout of the array is first made to an adjacent shift register with the readout of the shift register then being accomplished serially. Such apparatus is shown in the article entitled "Charge-Coupled Imaging Devices: Experimental Results" published by G. F. Amelio, et al., and appearing in the IEEE Transactions on Electron Devices, November, 1971, at pages 992-996, inclusive.
A charge sensing circuit is also disclosed by the prior art. Such apparatus is disclosed in U.S. Pat. No. 3,623,132, issued to Robert D. Green, and discloses a first field effect transistor being turned "on" during a first phase recurring interval for charging a first capacitor at the gate electrode of an output field effect transistor. During a second phase recurring interval, a second field effect transistor is turned "on" for coupling the first capacitor to a second capacitor at the output of a charge coupled circuit. The voltage on the first capacitor causes an inversion or depletion under the fixed plate of the second capacitor. If the charge coupled circuit is charged, that is it has minority carriers, an inversion region is formed under the fixed plate and electrically connects the second capacitor to the charge coupled circuit. Normally the charge coupled circuit is charged when a binary logic 1 is provided at the input to the circuit. If the inversion layer is formed, the voltage on the first capacitor is substantially reduced and the output transistor is turned "off." If the charge coupled circuit is not charged as when a logic 0 is provided at the input of the charge coupled circuit, the semiconductor substrate beneath the second capacitor plate is only depleted. The voltage on the first capacitor is reduced only slightly, and the output field effect transistor remains "on." The logic state of the charge coupled circuit is sensed by determining whether or not the output field effect transistor remains "on" or is turned "off."
The present invention is directed to a coherent sampling readout circuit and signal processor which provides time correlation of the output of each bit of a CCD shift register utilized in combination with a CCD line array for removing the Nyquist noise component and switching transients and comprises a multiplex MIS switch formed between the last bit of a CCD shift register and a reverse biased collecting diode, an MOS field effect transistor reset switch of first semiconductivity and a MOS field effect transistor amplifier of opposite type semiconductivity coupled to the collecting diode. A sample and hold circuit includes a first capacitor coupled to the output of the MOS amplifier and control signals are applied to the aforesaid circuit configuration for providing four timing sub-intervals during a charge transfer time period wherein the collecting diode is first reset to a predetermined reference voltage through the reset switch whereupon the circuit node capacitance between the collection diode, reset switch and the amplifier charges to a predetermined reset level. The sample and hold circuit then reads the predetermined reset level across the node capacitance and holds this level across said first capacitor. The MIS switch is then activated to gate out the minority carriers to the collection diode whereupon a difference signal is provided between the previously sampled reset signal level and the signal output from the collecting diode across a second capacitor.
FIG. 1 is a block diagram illustrative of the preferred embodiment of the subject invention utilized in combination with a charge coupled device array;
FIG. 2 is a partial cross sectional view of monolithic semiconductor charge coupled apparatus illustrative of a two-phase multilevel transfer electrode structure including a MIS output switch and a collecting diode;
FIG. 3 is an electrical schematic diagram of the preferred embodiment of the readout circuit forming the subject invention;
FIG. 4 is a more detailed partial cross-sectional view of a monolithic semiconductor device incorporating the readout circuit of the subject invention;
FIG. 5 is an electrical schematic diagram illustrative of the preferred embodiment of the subject invention;
FIG. 6 is a series of time related waveforms illustrative of the operative of the subject invention; and
FIG. 7 is a spectral noise power diagram helpful in understanding the subject invention.
Charge coupled devices (CCD) create and store minority carriers or their absence in potential wells which are spacially defined regions where depletion is momentarily deepened at the interface of a homogeneous semiconductor and oxide insulator. Once stored, the charges coupled to the potential well can be moved over the surface of the semiconductor simply by moving the potential well. The process of injecting charge into a semiconductor either by way of optical or electrical injection, transferring it by means of potential wells along the surface of the semiconductor and detecting it or its absence at some other location or some time later, forms the basis of the circuit operation.
Referring now to the drawings, attention is first directed to FIG. 1, wherein reference numeral 10 represents a linear charge coupled device array which may be operated as a line imaging device as taught by the above-referenced article entitled "Charge-Coupled Imaging Devices: Experimental Results." Minority carrier charge packets are formed at discrete positions along the array 10 in response to an optical signal hv impinging on each discrete region. A like number of transfer gates 12 simultaneously transfer all of the charge packets in the array 10 to a CCD shift register 14 when a gate signal .[.0T .]. .Iadd.φT .Iaddend.is applied to the transfer gates 12 prior to the beginning of a selected clock period T. The shift register 14 has a bit capacity equal to the number of discrete regions and transfer gates so that a separate bit receives a charge packet from its corresponding array element. The shift register 14 has an appropriate transfer electrode structure suitable for two phase operation. A two-phase clock, not shown, couples mutually 180° out of phase (anti-phase) square wave clock signals .[.01 and 02 .]. .Iadd.φ1 and φ2 .Iaddend.to the structure which sequentially shifts the charge packets to a multiplex (MUX) switch 16 which is operated in accordance with a control signal .[.0M .]. .Iadd.φM .Iaddend.synchronized to the clock signals .[.01 and 02 .]. .Iadd.φ1 and φ2 .Iaddend.. Thus a parallel to serial conversion is effected. The switch 16 sequentially gates minority charge packets from the last bit of the shift register 14 into a reverse biased output diode 18 which is periodically reset to a reference voltage VR by means of a MOS reset switch 20 operated in accordance with a reset signal .[.0R .]. .Iadd.φR .Iaddend.in a manner to be explained in greater detail subsequently. A MOS electrometer amplifier 22 then feeds into a sample and hold circuit 24 whose output comprises sequential video signals corresponding to the sequential output of the shift register 14.
Thus photons incident on the array 10 generate minority carriers which are stored in and moved therefrom through the transfer gates 12 to the shift register 14 which is indexed sequentially to the multiplexed output switch 16 which is adjacent the last transfer electrode, not shown. While the configuration shown in FIG. 1 is directed primarily to optical injection, it should be noted that any other desirable type of minority carrier generation, e.g., electrical injection can be utilized when desired.
Referring now to FIG. 2, a grounded substrate 26 of a first type semiconductivity (shown here illustratively as N type) is shown over which is disposed a dielectric layer 28 comprised of, for example, silicon dioxide SiO2. Transfer electrodes 30 and 32 form the last two transfer electrodes of the shift register 14 shown in FIG. 1. The transfer electrode configuration comprises multilevel elements which when desired, can overlap for two phase operation as taught in the prior art. Another metallic electrode 34 is also fabricated on the dielectric layer 28 adjacent the last transfer electrode 32 between the collecting diode 18 which is formed by a region of second type semiconductivity (P+ type) diffused in the substrate 26. An electrode 36 is formed at the innerface 38 between the insulating layer and the P+ type region 40. The transfer electrodes 30 and 32 are adapted to be coupled to anti-phase clock signals .[.01 and 02 .]. .Iadd.φ1 and φ2 .Iaddend., respectively, while the electrode 34 is adapted to be connected to a control signal .[.0M .]. .Iadd.φM .Iaddend.. It is the purpose of the gate electrode 34 and the SiO2 layer 28 to act as a switch for gating minority carriers or the absence thereof from the last potential well formed at the innerface 38 under the last shift register transfer electrode 32 to the collecting diode 18 which occurs when the signal .[.0M .]. .Iadd.φM .Iaddend. applied to the electrode 34 goes negative.
Referring now to FIG. 3 which discloses the additional readout circuitry employed, the reset switch 20 shown in FIG. 1 comprises an N channel MOS field effect transistor (FET) device fabricated on the same monolithic semiconductor structure shown in FIG. 2, while the electrometer amplifier 22 comprises a complementary P channel MOS field effect transistor device. A cross-section of the circuitry shown in FIG. 3 fabricated in an integrated circuit structure is shown in detail in FIG. 4. Referring now to FIG. 4, the N type semiconductor substrate 26 shown in FIG. 2, includes in addition to the P+ diffusion region 40, for forming the collecting diode 18, an N+ diffusion region 42 which acts as an isolation region. The P channel MOSFET electrometer amplifier 22 is fabricated between the collecting diode 18 and the N channel MOSFET reset switch 20 such that the P+ diffusion regions 44 and 46 define the source and drain respectively of the P channel FET while the gate electrode comprises a contact electrode 48 deposited on the oxide layer 28 overlapping the source and drain diffusions 44 and 46. The N channel MOSFET switch comprises N+ diffusion regions 50 and 52 which define the source and drain of an FET within a P type diffusion region 54. The gate electrode of the N channel MOSFET reset switch 20 comprises the contact electrode 56 deposited on the oxide layer 28 and overlapping the source and drain diffusions 50 and 52 with a metallization element 58 formed through a second oxide layer 29. The control signal .[.0R .]. .Iadd.φR .Iaddend. is adapted to be coupled to the gate of the MOSFET reset switch 20 through the metallization 58. A metallization 60 is coupled to the source diffusion region 50 through the oxide layers 28 and 29 and is adapted to have a reference reset potential -VR applied thereto. A common connection between the P+ diffusion region 40 of the collecting diode 18, the drain diffusion region 52 of the N channel MOSFET switch 20 and the gate electrode formed by the contact electrode 48 of the P channel MOSFET amplifier 22 is provided by the bridge type metallization 62. Ohmic contact of P channel amplifier 22 is obtained by means of a deposited metallization to obtain the output and -V terminals respectively.
Referring now to the schematic representation of the subject invention as shown in FIG. 5, the collecting diode 18 is shown having its cathode coupled to ground (substate 26 at ground potential) while the anode has a common connection between the drain of the N channel MOSFET reset switch 20 and the gate of the P channel MOSFET amplifier 22. This common connection (metallization 62 shown in FIG. 4) forms a circuit node 64 having a distributed capacitance CN to ground. A distributed capacitance CM also exists between the gate electrode 34 of the output MUX switch 16 and circuit node 64. Additionally, a distributed capacitance CF also exists between the gate electrode of the MOSFET reset switch 20 and the circuit node 64. These capacitances affect the operation of the circuit as will be subsequently shown. As already disclosed, a control signal .[.0M .]. .Iadd.φM .Iaddend.is applied to the switch electrode 34 and a reset control signal .[.0R .]. .Iadd.φR .Iaddend.is applied to the gate of the reset switch 20. The reset reference voltage -VR is applied to the source of the reset switch 20 while a slightly greater bias voltage -(VR +VEB) where VEB is equal to an emitter to base diode forward drop is applied to the substrate of the MOSFET reset switch 20. This substrate corresponds to the P diffusion region 54 shown in FIG. 4. The substrate of the N channel MOSFET reset switch 20 is biased slightly more negative than the source in order to avoid forward biasing the drain to substrate junction when the reset switch is turned off. For example, where VR = - 6 v and VEB =-0.7 v, if the voltage of .[.0R .]. .Iadd.φR .Iaddend.varies between 0 and -6.0 v, when the reset switch 20 is turned off, i.e., when .[.0R .]. .Iadd.φR .Iaddend. =-6.0 v, the effect of the capacitance CF and CN acting as a voltage divider causes a voltage corresponding to -6.0 [CF /(CF + CN)] =-0.2 v to appear at the circuit node 64 where typical value of CF and CN are in the order of 0.035 picofarads and 1.0 picofarads. Thus the circuit node voltage would go to -6.2 v i.e. -VR + (-0.2 v.) However with the increased bias, i.e., -6.7 v., applied to the substrate of the reset switch 20, the drain can never become more negative than the substrate. Thus when the reset switch is turned off, the circuit node 64 is a relatively high time constant voltage point which is provided by the node capacitance CN and the off resistance of the reverse bias collecting diode 18 and the drain to substrate junction of the reset switch 20.
With respect to the P channel MOSFET amplifier 22, the substrate is grounded since it actually is part of the N type semiconductor substrate 26 shown in FIG. 4. The drain electrode is coupled to a negative bias voltage -V and the output signal of the readout circuit is taken from the source of amplifier 22.
Referring now to FIG. 5, the output of the P channel MOSFET amplifier 22 is coupled to the sample and hold circuitry 24 by means of a preamplifier stage comprising an operational amplifier 66 and feedback resistor 68. The source electrode of the P channel MOSFET amplifier 22 is further biased by means of the potentiometer 70 coupled across a source of positive bias potential +V and a fixed resistor 72 coupled to the slider element of the potentiometer 70. The sample and hold circuit 24 includes a first or "clamp" capacitor 74 having one side coupled to the node capacitance CN through the output of the operational amplifier 66 while the other side is coupled to electrically controlled switch device 76 which may be, for example, a MOS switch. The switch 76 couples to a negative reference voltage -VC provided by a potentiometer 78 coupled across the voltage -V. The switch device 76 is adapted to be opened and closed in accordance with a synchronized control voltage applied to terminal 80 and depicted in FIG. 6. Circuit junction 82 which comprises the common connection between the capacitor 74 and the switch 76 is coupled to one input of an operational amplifier 84 which has another input connected to the reference voltage -VC at the potentiometer 78 which also acts as a clamping voltage or DC restorer voltage for the capacitor 74 and the operational amplifier 84. Additionally, the operational amplifier has a feedback network including resistors 86 and 88 coupled from the output of the operational amplifier to the same input to which the reference voltage -VC is applied. The output of the operational amplifier 84 is fed to a second electrically operated switch 90 which is opened and closed in response to another synchronized control voltage applied to terminal 92 (FIG. 6) as in the case of the electrically operated switch 76; switch 90, when desirable, may also comprise an MOS switch device. The switch 90 is coupled to a second or "sample" capacitor 94 which has its opposite side returned to ground. Circuit junction 96 which forms the common connection between the electrically operated switch 90 and the capacitor 94 is coupled to another operational amplifier 98 which has a feedback network including the variable resistor 100 and fixed resistor 102 coupled from the output to another input thereof. The output of the operational amplifier is connected to a circuit terminal 104 which is adapted to provide a video output signal of the minority carrier charge packet fed into the collecting diode 18.
The operation of the readout and signal processor circuitry can best be understood in light of the timing signals indicated by the time related waveforms shown in FIG. 6. There are four distinct timing subintervals in each time clock period T, that is the time within which the two phase clock system steps each charge packet from one transferred electrode to another in the shift register 14 shown in FIG. 1. While each charge packet is being shifted, the last or output bit of the shift register is being read out and processed by the circuitry shown in FIG. 5. The timing diagram shown in FIG. 6 first discloses waveform 106 which corresponds to the control voltage 0T which periodically effects the parallel transfer of all the minority carrier charge packets from the CCD array 10 to the shift register 14 by means of the transfer gates 12. This waveform is a negative going waveform and occurs prior to the beginning of the anti-phase clock voltages .[.01 and 02 .]. .Iadd.φ1 and φ2 .Iaddend.shown by waveforms 108 and 110, respectively. It is to be observed that the second clock voltage .[.02 .]. .Iadd.φ2 .Iaddend.is applied to the last transfer electrode 32 of the shift register (FIG. 2). A charge packet from the next to last bit of the shift register will not be transferred to the last bit until the potential well under the last transfer electrode 32 goes further negative which is after one half of a clock period T. During a portion of the first half of the clock period T a reset control signal .[.0R .]. .Iadd.φR .Iaddend.applied to the gate of the N channel MOSFET reset switch 20 goes high, i.e., from -6.0 volts to 0 volts as shown by waveform 112. When the waveform 112 goes to 0 volts, the N channel MOSFET reset switch 20 is turned "on" and the node voltage VG which appears across node capacitance CN goes to the reference voltage -VR after an initial transient ΔV= CF (VR - VT)/(CF + CN) where VR = -6.0 v and VT = 2.0 v, the device threshold voltage. After the switching transient RON CN ≈ 10 nanoseconds the circuit node voltage is equal to -VR which charges the node capacitance CN. In charging the node capacitance CN, the voltage -VR has an uncertainty expressed by the Nyquist voltage (Vn 2)1/2 = (kT/CN)1/2 wherein k is equal to Boltzman's constant, T is the temperature, and CN is the node capacitance.
The reset signal .[.0R .]. .Iadd.φR .Iaddend.is next removed by making .[.OR .]. .Iadd.φR .Iaddend.again go to -6.0 volts. Since the collecting diode 18 is reverse biased, and MOSFET switch 20 is now "off," the discharge time constant of the node capacitance CN becomes extremely long (in order of 10 seconds with respect to the clock period T (typically less than 100 microseconds). Thus the node capacitance CN will maintain the charge corresponding to the reference voltage -VR ± (Vn 2)1/2. This defines the first subinterval called the "reset" time. Following this, the second subinterval comprises the application of a low going control voltage shown .[.76.]. by waveform 116 to the electrically controlled switch 76 in the sample and hold circuit 24 which closes. Capacitor 74 is thus connected across the node capacitance CN and charges to the voltage thereacross while being clamped to the voltage -VC. The waveform 116 then returns to a zero level opening the switch 76. The opening of switch 76 by waveform 116 ends the second subinterval which is defined as the "read reset" time causing the voltage across capacitor 74 to be such that the voltage -VR - ΔV± (Vn 2)1/2 = V2 applied to the node capacitor CN is read and clamped. Next a negative or low going control signal .[.0M .]. .Iadd.φM .Iaddend.as shown by waveform 118 in FIG. 6 is applied to the MUX switch electrode 34 (FIG. 2) whereupon the minority carrier packet in the potential well under the last bit transfer electrode 32 is transferred to the reversed biased collecting diode 18. The collection of minority carriers causes the voltage across the node capacitor CN to change by a voltage
ΔV.sub.M = [C.sub.M /(C.sub.M + C.sub.N)]V.sub.M
where VM is the voltage amplitude of the "MUX" signal .[.0M .]. .Iadd.φM .Iaddend.shown in FIG. 6. The voltage on the circuit node 64 during this subinterval is
V.sub.S - V.sub.R - ΔV- ΔV.sub.M ± (V.sub.n.sup.2).sup.1/2
as shown in FIG. 6, where VS is the signal voltage. Assuming that the CCD array 10 is an imaging array and the instant charge packet corresponds to a dark level, the voltage at VG will decrease as shown by waveform 114 whereas if the bright signal appears, the voltage VG will tend to go more positive. The control signal .[.0M .]. .Iadd.φM .Iaddend.is then removed ending the third subinterval defined as the "minority carrier signal input" time. When the "MUX" signal .[.0M .]. goes from - Vm to 0 as shown in FIG. 6, a charge is removed from circuit node 64 corresponding to +ΔVM. Thus the switching transient charge is removed from the signal processing which increases the dynamic range of the processor. During the "read minority carrier signal" subinterval the voltage level of the circuit node 64 is -VR -ΔV± (Vn 2)1/2 + VS = V4 where VS = Qs /CN is the signal input determined by the signal charge Qs. After the MUX switch 16 is turned off, the output voltage across capacitor 74 consists of a time correlated difference signal between the input signal plus the reset level and the reset level due to the fact that the switch 76 is now in the open state. The fourth or "read minority carrier signal" subinterval occurs after the MIS switch 16 is turned off and a negative or low going control signal is applied to the second switch 90 by means of a signal corresponding to the waveform 120 shown in FIG. 6 being applied to terminal 92 whereupon the switch 90 closes. Since there is negligible leakage of the reset level at circuit node 64 due to the extremely long discharge time constant ROFF CN provided by node capacitance CN and the off resistance provided by the non conducting drain to substrate junction of MOSFET 20 and reversed biased collecting diode 18, closure of switch 92 results in a sampled voltage appearing across capacitor 94 which is a measure of the time difference between the signal plus the reset level minus the reset level, i.e., V4 - V2 = [-VR - ΔV+ Vs ± (Vn 2)1/2 ]-[-VR -ΔV± (Vn 2)1/2 ]= Vs . What is significant about the operation thus described, is that the sampled noise, i.e., the Nyquist voltage uncertainty at the "read reset" time is the same as sampled at the "read minority carrier signal" time. Thus the noise is said to be correlated.
With this method of signal processing several important advantages are derived which is particularly important for low light level detection in an imaging array. First of all, switching transients are removed since the feedthrough voltage is sampled and held during the "read reset" subinterval when the reset switch 20 is turned off. Likewise, the stored feedthrough charge transient from the on-going switch 16 is "pulled-out" when the switch is turned off. Secondly, the sampling and holding process moves the Nyquist noise component since the charge packet signal voltage from the shift register is multiplexed onto a known reset level, that is the previously sampled and held reset level -VR - ΔV± (Vn 2)1/2 the noise voltage contribution from the reset switch is removed in the time difference operation. In other words, a time correlation method of removing the Nyquist noise has been provided. The subject invention also provides dark level subtraction to increase dynamic range and provide uniformity across the array. The video signal is clamped to a reference voltage -VC which is analogous to DC restoration in pick up tubes.
The analog signal processor has another important feature in that it can reduce the l/f noise component in the signal, collection diode, reset switch and electrometer amplifier. In order to understand this, a simple analysis can be performed to show that the processor transfer function can be written as:
|H(ω)|.sup.2 = H.sub.o (Sin.sup.2 ωI.sub.o)/2/(1 + ω.sup.2 R.sup.2 C.sup.2) where ω= 2πf,
where Ho is adjustable gain, To is the time diffrence between read operations as shown in FIG. 6 and RC the time constant of the preamplifier 66 shown in FIG. 5. If l/f noise is present, then the above transfer function will depress the noise power spectra at low frequencies while allowing the signal to pass unattenuated and amplified. FIG. 7 illustrates this concept wherein curve 122 depicts the l/ω noise power spectra at the processor input, curve 124 is illustrative of the noise power spectra at the processor output and curve 126 denotes the transfer function |H(ω)|2.
In summation therefore, the subject invention is directed to readout and signal processor circuitry for a parallel to serial conversion CCD array wherein the white noise, i.e., Nyquist noise, is first measured and then the signal level itself including the white noise is measured. A subtraction of the two is then provided which removes the noise in a time correlation process within the same clock period.
Having thus disclosed what is at present considered to be the preferred embodiment of the subject invention:
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|U.S. Classification||377/60, 257/248, 327/552, 327/91|
|International Classification||G11C27/04, H01L27/148, G11C19/28, H01L29/768|
|Cooperative Classification||H01L29/76816, G11C27/04, H01L27/14831, G11C19/285|
|European Classification||G11C19/28B2, G11C27/04, H01L27/148C, H01L29/768C|
|Jul 16, 1996||AS||Assignment|
Owner name: NORTHROP GRUMMAN CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WESTINGHOUSE ELECTRIC CORPORATION;REEL/FRAME:008104/0190
Effective date: 19960301