US RE30187 E Abstract Error correcting apparatus is provided for correcting plural channels in error in a parallel channel information system. The information is encoded in a cross-channel direction as well as along the channel length. The encoded message after storage or transmission is decoded in the cross-channel direction and error correction provided in the in-channel direction in a given number of indicated channels. Orthogonally symmetrical redundancy enhances error correction while tending to minimize hardware. Plural independent codes interact to correct the plural channels in error. The error correcting capabilities of the codes may be matched, no limitation thereto intended.
Claims(50) 1. An error correcting system for correcting up to two channels in error in a multiparallel channel data handling system comprising:
an encoding system including cyclic check bit generating means for generating an orthogonally symmetrical check bit for each of said parallel channels, said check bits being entered into said respective channels and being grouped to form a cross-channel check byte; said encoding system further including parity bit generating means for generating parity bits for information bytes formed in a cross-channel direction, means for entering said parity bits into one of said parallel channels; means for decoding said data by means of said parity bits and information bytes formed in the cross-channel direction to detect errors; and means for correcting errors in all the bytes extending along any one or more channels including cyclic means generating a cyclic syndrome vector simultaneously to a parity syndrome vector based on the errors detected in the decoding utilizing only said cross-track bytes. 2. An error correcting system according to claim 1, wherein said parity bit generating means generates another parity bit for each of said groups of check bits forming a cross-channel byte so that said means for decoding is applicable to said cross-track check byte and said means for correcting errors includes the said check bits in any one or two designated channels of said parallel channels.
3. An error correcting system according to claim 1, wherein said means for generating check bits including means for computing said cross-track check bytes according to the relationship:
C=TB where T is the companion matrix of an irreducible binary polynominal g(x) of degree n _{2} and T^{i} represents the i^{th} power of the matrix T and B_{i} represents the n_{2} data bytes of n_{1} -1 bits.4. An error correcting system according to claim 3, wherein said means for generating check bits includes a shift register which premultiplies the incoming bytes by T.
5. An error correcting system according to claim 3, including means in said decoder for computing two syndrome bytes S
_{1} and S_{2} each of n_{1} -1 bits according to the relationship:S which is derived from modulo 2 addition of the generated parity byte P and the received parity byte P; and S wherein an underlined symbol indicates a byte of said received message corresponding to nonunderlined symbols in said sent message. 6. An error correcting system according to claim 5, wherein said means for computing two syndrome bytes S
_{1} and S_{2} includes feedback shift registers, said shift register for computing S_{2} being a backward shifting register having a premultiplier T^{n}.sbsp.2.7. An error correcting system according to claim 1, means supplying error location pointers, said means for decoding includes an N indicator means for providing the control signal N
_{1}, N_{3}, and Q in response to error pointers indicating the channel in error, the N_{1} signal indicates that only one channel pointer or none are on, the N_{3} signal indicates that more than two channel pointers are on, and the Q output represents the pointers Q_{0} -Q_{8}, and means for inhibiting said control signals Q when N_{1} or N_{3} is on.8. An error correcting system according to claim 7, wherein said means for decoding further includes means for generating the error track parameters I, i, and j-i from the pointer control signals Q, the error channel parameter I being a new pointer which identifies the first erroneous data channel called the I
^{th} channel, the signals i being generated as binary numbers from the I pointer signals and the j-i signals indicating the responsive distance of the channels in error.9. An error correcting system according to claim 8, wherein said means for decoding includes means for generating the error pattern e
_{2} from the S_{1} and T^{-i} S_{2} inputs controlled by said j-i inputs according to the relationships:e where: M if j-1≠0 and j≠8 M if j-i=0 or j=8 and I _{d} is an identity matrix.10. An error correcting system according to claim 9, wherein said means for decoding includes means for generating a code pointer Q' and means for generating a count R, said means for generating a code pointer having the count R, the control signal N
_{1}, and e_{2} as inputs; said code pointer generator generating the code pointer Q' indicative of a single track in error when said input signal e_{2} =0 and N_{1} is on, the R count from said ring counter indicating the channel in error.11. An error correcting system according to claim 1, wherein said means for correcting errors in all the bytes extending along any one channel or any two designated channels includes modulo 2 adder circuits for comparing the error patterns S
_{1} and e_{2} with said channel bytes of information Z_{0}, Z_{1}, Z_{2}, . . . Z_{7} and producing corrected information in accordance with said error patterns to obtain the corrected information Z_{0}, Z_{1}, . . . Z_{7}.12. The method of transferring successive N-bit signal bytes through N channels, one signal from each byte in a channel, including the steps of:
A. at a transmitter, 1. collecting N-1 data signal bytes; 2. generating a check bit signal byte for said N-1 data signal bytes in an orthogonally symmetrical manner; 3. transferring said N-1 data and check bit signal bytes as a signal set over said N channels; repeating (1), (2), and (3) until signals have been transferred; and B. at a receiver for said transferred data signal bytes in each said set, 4. computing a second check bit signal byte supposedly identical to said transferred check bit signal byte; 5. comparing the check bit signal byte and from said comparison generating an error pattern for signals along a given channel; 6. indicating which channel is said given channel having signals in error; and 7. applying said error pattern to correct signals in said given channel for such signal set. 13. The method set forth in claim 12 further including the steps of:
A-1. at the transmitter, 8. generating an independent check bit signal for each of said bytes including said check bit signal byte as they are being transferred; B-1. at the receiver, 9. combining said independent check bits for all of said bytes in a given signal set with said check bit signal byte for generating first and second error pattern signals respectively for first and second chanels; 10. repeating step (6) for each signal set for indicating which two channels have signals in error; and 11. selectively modifying step (7) to correct signals in two of said channels rather than correcting errors in but one channel for such signal set. 14. The method set forth in claim 12 further in said step (2) generating said check bit signal byte in accordance with an identity matrix and N-1 companion matrices, each matrix consisting of n column vector operator signals modulo a selected polynomial; and
B-2. at said receiver, 12. processing said data bytes in each said channel such that the operational relationships between each and every data bit and each and every check bit with respect to said column vector operators remain the same even though the signals are along the respective channels. 15. The method set forth in claim 14 further including selecting said independent check bit signal to be a parity signal and selecting a magnetic tape unit having nine tracks with a central one of said tracks being the parity track and the other eight tracks, including the outside tracks, being data tracks, and repeatedly performing said steps (1) through (3), (8) for recording a plurality of successive end bit signal bytes on said tape and repeatedly performing steps (4) through (7) and (9) through (12) for reading back the signals recorded on such tape.
16. The method of operating a multichannel digital signal apparatus,
including the steps of: selecting a first group of said channels to sequentially transfer plural sets of data signals, the number of signals in each channel for each set being one less than the number of channels in said first group; for each said set, generating a first check byte having one signal in each channel for said each set of said first group and arranging all signals in each said set including said check byte signals to have orthogonal symmetry; and generating second check signals based on said arranging and supplying said second check signals to a channel other than said first group of channels. 17. The method set forth in claim 16 selecting a polynomial from the Galois Field 2
^{b} for said first check byte, where b is the number of channels in said first group and generating said second check signals in a manner not describable in terms of symbols in said Galois Field 2^{b}.18. The method set forth in claim 16 including generating said second check signals as parity signals based upon one signal from each of said channels in said first set and aligned in a cross-channel direction.
19. The method of operating a multichannel digital signal transfer system,
including the step: selecting first and second independent error correction codes, each having a given error correction capability, said first error correction code exhibiting orthogonal symmetry; dividing the digital signals into sets along the respective channels into a number of signals less than the number of channels; establishing a first check bit byte in accordance with a given orthogonal symmetry and a polynomial in said first error correction code; establishing a second check bit byte in accordance with said second error correction code; and selectively using one or both of said codes to correct errors in a given one of said channels. 20. The method set forth in claim 19 including selectively using both of said codes to correct errors and including shifting data signals in the respective sets in a forward direction for processing signals in a so-called forward direction including premultiplying by a matrix T of said polynomial, then repeatedly matrix multiplying by a matrix T by shifting in a forward direction and including linear feedback in said shifting in accordance with said polynomial; and
selectively processing said signals in a backward direction including premultiplying said signals in the respective sets by a matrix T ^{7} of said polynomial and including matrix multiplying said signals in such sets by T^{-1} for seven times in a so-called backward direction.21. The method set forth in claim 19 further including selecting said first independent error correction code to have orthogonal symmetry in accordance with a given polynomial and arranging column vectors based upon said polynomial in a predetermined manner such that said check bit signals mathematically established said check bit byte in a predetermined relationship to the data signals in a cross-channel direction, a first position being an end position of an array including said data signals and said first check bit byte signals.
22. The method set forth in claim 21 further including selecting said column vectors to generate error correction and error bit generating matrices for placing said check bit byte in a central position of said data signals array rather than in said end position.
23. The method of generating a check bit to establish orthogonal symmetry in a set of data and check signal bytes, each byte having N-1 bits and the set having N bytes, N being a positive integer greater than 1,
including the following steps: arranging the signals in a rectangular array; selecting one of the diagonals of said rectangular array as a line of symmetry; selecting a bit position of said check byte for a check bit signal to be generated; generating the selected check bit signal by modulo 2 adding signals in the array along selected ones of diagonals transverse to said line of symmetry, the signals on said transverse diagonals being either on said line of symmetry or symmetrically disposed with respect to said line of symmetry and selecting one of said selected diagonals in accordance with the location of said selected check bit signals in said array and adding said signals symmetrically except for said check bit signal to be generated. 24. The method of claim 23 including generating the seleceted check bit signal by modulo 2 ending all signals along said selected transverse diagonals except said check bit signal in one of said selected diagonals.
25. The method of claim 23 further including the step of selecting said check bit position and then selecting all said transverse diagonals in a sequence proceeding from said one transverse diagonal in but one direction along said line of symmetry.
26. Error correcting apparatus for processing data and check bit signals received from a multichannel signal transfer system, said signals in said channels being grouped into multichannel signal sets having a number of signals along each channel equal to the number of channels, all signals in one channel being a first check bit redundancy portion and one signal of each set in each remaining channel being a signal in a second check bit redundancy portion, said data signals and second check bit redundancy signals exhibiting orthogonal symmetry,
the improvement including in combination; first byte signal processing means for calculating said first check bit redundancy based on received signals from said remaining channels and comparing same with received first check bit redundancy signals from said one channel to supply first syndrome signals; second byte signal processing means for each signal set for simultaneously processing one signal from each of said remaining channels to compute said second check bit redundancy and compare a received second redundancy signal with calculated second check bit redundancy to supply second syndrome signals; means storing received signals from said remaining channels; means receiving said syndrome signals and having orthogonally symmetrical matrix multiplication means to generate an error pattern for signals in error along any one of said channels in one of said signal sets; and means receiving said stored signals and said error pattern for correcting signals in error, if any, along one or more of said channels. 27. The error correcting apparatus set forth in claim 26 including forward signal processing indicating means and backward signal processing indicating means;
means in said second byte signal processing means responsive to said forward processing indicating means to premultiply said data signals on a byte basis by a matrix T based upon a polynomial for said second check bit redundancy portion and effectively forward shifting said signals to multiply by said matrix T and including linear feedback means during said second byte signal processing; means in said second byte signal processing means responive to said backward byte processing indicating means to premultiply said data signals by the matrix T ^{7} and further having means operating said second byte signal processing means for effectively shifting said signals in a backward direction such that each shift is equal to a matrix multiplication of T^{-1} ; andall of the other means in said error correcting apparatus being responsive to said forward and backward indicating means, respectively, to alter operations to accommodate forward and backward signal processing. 28. The apparatus set forth in claim 27 further including means in said syndrome receiving means indicating when said one channel is in error and operation altering means responsive to indicating that said one channel is in error not to correct said one channel; and
means generating an indication of which data channel is in error and said error correcting means being jointly responsive to said second byte signal processing means and said error pointer means to correct data signals in error independent of signals from said one channel. 29. The error correcting apparatus set forth in claim 26 wherein said second byte signal processing means generates a set of output signals equal to T
^{-i} S_{2} ;error pattern generator means responsive to said T ^{-i} S_{2} and to said first byte signal processing means for generating a given error pattern;counter means responsive to the number of bytes being processed to supply an R count; code pointer generator means jointly responsive to said R count and said given error pattern to generate a track-in-error pointer signal; error track parameter generator responsive to said code pointer generator and having error pointer means for generating a set of track-in error pointer signals and error correcting means jointly responsive to said given error pattern and to said track-in-error indicator to correct errors along a given channel wherein said given error pattern is used both to indicate a track in error and the error pattern along such track; and wherein said error correction means is further responsive to said first byte signal processing means to correct a second channel in error in accordance with pointer signals received from said error track parameters generator. 30. An error correction signal generating system for a multichannel digital transfer system, a first plurality of said channels transferring data representing digital signals,
the improvement including in combination: means grouping data representing digital signals along each channel in signal groups having a number of signals equal to a number less than said first plurality; means associating all groups in said channel together as a multichannel signal set; means calculating check bit redundancy signals for all signals in one signal set; means for transmitting a first portion of said redundancy signals along a channel not in said first plurality of channels and means for transmitting a second portion of said redundancy signals as one signal in each of said first plurality of channels; and said calculating means establishing an orthogonal symmetry between said data signals and said second portion of said redundancy signals in each said signal set. 31. A signal transfer system having error detection and correction capabilities, including in combination:
a signal transfer apparatus having a given error mode; data signal means connected to said apparatus for exchanging data signals therewith; first means interposed between said apparatus and said data signal means for selecting a given number of said data signals and including means grouping said selected data signals into a plurality of channel bytes to form an error correcting signal set; error signal means in said first means receiving said data signals as cross-channel signal bytes, such cross-channel bytes having one data signal from each said channel bytes in accordance with a rectangular array of signals having one more signal along one dimension of said array than another dimension, redundancy means in said error signal means generating a redundancy signal byte having a number of check bit signals equal to the number of signals along said one dimension and operating on said signals as a square signal array with said redundancy signal byte in said array being parallel to said another dimension, means in said redundancy means relating each of said check bit signals to a unique group of said data signals such that all related signals (each check bit signal and its associated unique group of said data signals) exhibit orthogonal symmetry about a predetermined diagonal of said square array; and means in said first means exchanging a redundancy signal byte between said error signal means and said apparatus. 32. The system set forth in claim 31 further including second error signal means in said first means for each signal set independently generating a separate second check bit signal on all signals in each said cross-channel bytes, plus a second check bit signal on said redundancy byte; and
means exchanging all said second check bit signals between said signal transfer apparatus and said second error signal means. 33. The system set forth in claim 32 including error correction means receiving said data signals, said redundancy byte, and all said second check bit signals and for each said signal set for combining same to generate signals pointing to at least one of said bytes as being in error, if in error, and error pattern means selecting said redundancy byte exchanged with said signal transfer apparatus to indicate which bits of said byte in error are in error.
34. The method of arranging data signals and generating check redundancy signals in connection with transferring digital data signals, including the steps of:
dividing said digital data signals into successive signal sets, dividing each said signal set into a given plurality of channel bytes, the number of said digital data signals in each channel byte being one less than said given plurality; generating a first check redundancy signal byte having a number of signals equal to said given plurality and based upon a given error correcting polynomial of the irreducible type; generating a second check redundancy signal byte to have said given plurality of byte check bit signal portions, selecting signals from each said channel bytes and said first check redundacy signal byte to generate said check bit signal portions, respectively; and transferring said signal set and said first and second check redundancy signal bytes as a set of digital signals. 35. The method set forth in claim 34 further including the steps of:
taking transferred signals and generating new first and second check redundancy signal bytes therefrom; and combining transferred first and second check redundancy signal bytes with said new first and second check redundancy signal bytes to generate pointer signals pointing to bytes in error and error pattern signals pointing to individual transferred data signals in said bytes in error for enabling correction of said individual signals. 36. The method set forth in claim 35 further including the steps of evaluating signal transfer and pointing to bytes possibly being in error based upon such evaluation; and
selectively modifying said combining of said check redundancy signal bytes in accordance with said error possibility pointing for correcting a greater number of signals than without such error pointing. 37. The method of preparing digital signals for recording such digital signals comprising the steps of:
selecting a set of digital signals to be recorded, dividing said set into a given number less one of channel bytes, each channel byte having said given number of digital signals; generating a check byte of said given number of signals in an orthogonal symmetrical manner for each digital data signal set; independently generating a second check byte having an independent portion for groups of signals having one signal from each said channel byte and one portion for said check byte; and recording all signals of one set including said check bytes as a separate record entity. 38. The method of reading correcting errors in digital signals read from a record member having recorded digital signals arranged in sets, each set having a predetermined number of digital data signals, a first redundancy signal subset exhibiting orthogonal symmetry with said digital signals in said set and a second redundancy signal subset in said set not exhibiting said orthogonal symmetry with said digital data signals but exhibiting a second error correcting characteristic, reading said signals from said record member,
the method including the steps of: generating new first and second redundancy signals from digital data signals read from said record member, such new redundancy signals matching recorded redundancy signals in an error-free condition; comparing said new first and second redundancy signals with first and second redundancy signals read from said record member and generating an error location signal from said comparison showing that such error, if any, is in a given group of signals and error pattern signals showing which signals in such group are in error; and changing the signals in error. 39. The method of preparing digital data signals for recording in a block of such signals in a multitrack record member,
the method improvement including the steps of: 1. selecting a set of data signals to be recorded with one signal in each channel for forming a cross-channel byte; 2. arranging said bytes into sets of one less than the number of channels of said cross-channel bytes; 3. generating a check cross-channel byte on said set of cross-channel bytes; 4. recording said cross-channel bytes of (2) and (3); and 5. repeating (1)-(4) until all signals to be recorded in a block have been recorded. 40. The method of claim 39 further including the steps of generating a parity signal for each cross-channel byte independent of said check cross-channel byte generating indicating parity on such check cross-channel byte and recording such parity signals in one channel.
41. The method of correcting signals in error in a set of digital data signals; including the steps of:
arranging the signals in a rectangular array of channel bytes along a first array dimension and cross-channel bytes along a second array dimension; generating a check byte redundancy by successive byte calculations along one array dimension; generating a first set of syndrome signals and error pattern signals from said redundancy and data signals along said one array dimension; and correcting errors by applying said error pattern signals to data signals in one byte extending along a second one array dimension. 42. The method set forth in claim 41 further including the steps of:
generating a second redundancy along said second one array dimension independently of said first redundancy but having a check portion based upon said first redundancy; generating a second set of syndrome signals based upon said second redundancy and said data signals and said first redundancy, and a second set of error pattern signals; and simultaneously applying said error patterns to two bytes, respectively, extending along said second one array dimension. 43. The method set forth in claim 42 and practiced in part in a linear feedback shift apparatus,
the method of arranging said signals into said array including loading said bytes along said one array dimension serially into said shift register while synchronously shifting same and feeding back in accordance with a selected irreducible polynomial; storing said loaded bytes fed to said shift register in a storage apparatus; and applying said error pattern signals serially to selected two signals in each said loaded bytes while synchronously transferring such bytes from said storage apparatus. 44. A code circuit for a multichannel signal processing apparatus which processes a given number of signals from each channel as a group of signals, a check character set of signals being included in said group of signals and having one signal in each said channels,
a multichannel network realizing polynomial g(x) and receiving said given signals in seriatim from said apparatus, one signal at a time from each channel in parallel with one signal from others of said channels after generating a syndrome character representative of errors in said given signals; first means indicating a single channel in error, means responsive to said indication for applying said syndrome character to said channel in error as an error pattern for correcting said given signals in said channel in error. 45. The circuit set forth in claim 44 further including a parity channel in said apparatus having a given number of parity signals associated with said group of signals, the improvement further including in combination:
second means in said first means indicating two channels in error and means inhibiting said first means indications when two channels in error are indicated, and means receiving said parity signals and said given signals to generate a parity syndrome character, means responsive to said second means to apply said syndrome characters as error patterns to respective ones of said two channels in error for correcting signals in said channels in error. 46. Code circuits for multichannel signal apparatus, including in combination:
a check character generator circuit means realizing polynomial g(x) and generating a check character based upon received signals from all channels and means supplying said check character with one signal in each of said channels, first circuit means supplying successive sets of signals in parallel to said generator circuit, second circuit means responsive to a given number of said successive sets of signals being supplied to activate transfer of said check character as a check set of signals interleaved among said sets, control means for repeatedly activating said circuit means to generate a train of signal sets in all channels including interleaved check sets, and receiver means responsive to said check sets and associated ones of said sets of signals to correct signals in any one of said channels. .Iadd. 47. Apparatus for identifying and correcting errors in one or two tracks of digital information derived from a multi-track medium, bits of data from ones of the tracks forming a byte, said tracks including a parity track, said bytes including n data bytes D _{1} -D_{n} and an error checking code ECC byte of i bits, said error checking code ECC being related to said data bytes according to the relation ##EQU8##.Iaddend. comprising:logic means for operating sequentially upon each of n received data bytes and an ECC byte to produce an error term E, said error term being equal to zero in the absence of errors in the received data and ECC bytes; second logic means for regressively operating upon said error term -i times to produce the vector EC ^{-i} ;means for accepting signals representative of data bits of the digital information and responsive thereto for deriving a parity character P _{n} which in combination with a data byte D_{n} produces an even number of data bits of a first kind;combining means for logically combining a regressed error vector and a parity vector P _{n} on a bit-by-bit basis to form the expression EB^{-i} +P_{n} ;a data correction matrix; parity correction logic means coupled to said logic means and to said means for accepting for receiving an error vector and a parity vector and operative to apply a signal to said data correction matrix to correct the ith data track to conform with said parity vector when said regressed error vector equals said parity vector; means for receiving track pointers indicating the presence of errors in ones of said tracks and for disabling the correction apparatus when three or more tracks are in error; track separation logic means coupled to said means for receiving and responsive to track pointers for identifying the separation (i-j) between a most significant track i which is associated with a lower-order polynomial term and a least significant track j which is associated with a higher-order polynomial term of the polynomial m=1 n=7 ΣD m=7 n=1 a divisor generator coupled to said track separation logic for selecting the term 1+B ^{-}(i-j) in accordance with track separation (i-j);dividend logic means for dividing said regressively operated vector by the output of said divisor generator to produce an error vector e _{nj} for data in the least significant track j in error;logic means for combining on a bit-by-bit basis said derived parity character P _{n} and said error vector e_{nj} to produce an error vector e_{ni} for data in the most significant track i in error;means for associating said error vectors e _{ni} and e_{nj} with the data tracks i and j respectively; andsaid data correction matrix receiving uncorrected data and said error vectors and combining said data and said vectors to invert the polarity of erroneous bits of said uncorrected data in accordance with the characteristics of said error vectors. .Iadd. 48. The invention defined in claim 47, further including:
means for receiving a pointer indicative of an error in a received parity track P; and means for correcting said parity track to correspond to said error vector e _{ni}. .Iaddend. .Iadd. 49. Apparatus for identifying and correcting errors in one or two tracks of digital information derived from an encoded medium, said tracks including a parity track, each track being encoded with bits, each bit being associated with another bit from each track to form a byte, said bytes comprising data bytes D_{1} -D_{n} and an error checking byte ECC, said error checking byte being related to said data bytes according to the relation ##EQU9##.Iaddend. comprising:first logic means for operating sequentially upon each of n received data bytes and the error checking byte according to an operator B to produce an error term E, said operator B being such as to produce the error checking byte by sequentially operating upon data bytes D _{1} -D_{n} said error term being equal to zero in the absence of errors in the received data and error checking bytes;second logic means for regressively operating i times upon said error term according to the operator B to sequentially produce error vectors e _{nl} through e_{ni} ;means responsive to bits encoded on the parity track of the digital information for generating parity vectors P _{n} which when combined with a received byte and associated parity term produce an even number of data bits of a first kind;means for sequentially combining ones of said error vectors with ones of said parity vectors; separation logic means for receiving track pointers indicating the existence of errors in two identifiable tracks and producing output signals in response thereto; track separation logic means coupled to said separation logic means and responsive to said output signals for identifying the separation between the most significant and least significant tracks in error; divisor generator means coupled to said track separation logic means for outputting a divisor expression; means for dividing ones of the combined error vector e _{ni} and parity vector by said divisor expression to produce an error vector for data in the least significant track in error;means for additively combining said least significant track error vector and said parity vector to produce an error vector for data in the most significant track in error; and a matrix for associating each of said error vectors with appropriate ones of said tracks in error and for correcting erroneous data bits in said tracks in accordance with said error vectors. .Iadd. 50. Apparatus as set forth in claim 49, further including sequence inversion means coupled to said first logic means for inverting the order in which tracks of data bits are received by said first logic means. .Iaddend..Iadd. 51. Apparatus as defined in claim 50, further including means for rendering said identifying and correcting apparatus inoperative when track pointers indicating errors in three or more tracks are present. .Iaddend..Iadd. 52. Apparatus as defined in claim 51, further including means for receiving a pointer indicative of an error in a received parity track; and
means for correcting said parity track in conformity with the error vector for said most significant track in error. .Iaddend. .Iadd. 53. Apparatus as defined in claim 52, wherein said matrix for associating includes a first plurality of inputs, further including: means for sequentially applying bytes of uncorrected received data to said first plurality of inputs; said matrix for associating comprising a data correction matrix including said first plurality of inputs and further having a second plurality of inputs, one input for each data track; a most significant track correction vector matrix having a plurality of outputs coupled to said second plurality of inputs, and having inputs coupled to said means for additively combining and to said means for identifying said most significant track in error, for combining an error vector signal and a track identification signal and outputting a correction signal upon one of said outputs coincidentally with the transfer of a byte having an erroneous data bit in the most significant track in error to said data correction matrix; and a least significant track correction vector matrix having a plurality of outputs coupled to said second plurality of inputs, and having inputs coupled to said means for dividing and to said separation logic, for combining an error vector signal and a track identification signal and outputting a correction signal upon one of said outputs coincidentally with the transfer of a byte having an erroneous data bit in the least significant track in error to said data correction matrix. .Iaddend. .Iadd. 54. The method of identifying and correcting errors in one or two tracks of digital information derived from an encoded medium, said tracks including a parity track, each track being encoded with bits, each bit being associated with another bit from each track to form a byte, said bytes including n data bytes and an error checking code byte, comprising: operating n+1 times upon n sequentially received data bytes and an error checking code byte in accordance with the operator B, said operator B being that operator used to develop the ECC byte in the encoded data, to produce an error term E; generating a local parity signal to provide an even number of data bits of a first kind for each received data and error checking code byte including a received parity bit; regressively operating upon error term E with the operator B a number of times i to sequentially produce error vectors e _{n1} -e_{ni} ;combining each sequentially produced error vector with ones of said parity vectors; detecting a coincidence between an error vector and a parity vector; and correcting the track of received data whose position corresponds to the number of regressive operations needed to achieve correspondence between said error and parity vectors, in accordance with the error vector so achieved. .Iaddend..Iadd. 55. The method defined in claim 54, further including the steps of
detecting the occurrence of n+1 regressive operations in which no coincidence between an error vector and a parity vector has occurred; detecting the presence of two tracks of received data in which errors may have occurred and identifying the tracks; dividing the combined error vector e _{ni} for the most significant track in error and the associated parity vector by a term which is a function of the separation of the two tracks in error to produce an error vector e_{nj} for the least significant of said tracks;associating the least significant track error vector e _{nj} with the least significant track in error;associating the most significant track error vector e _{ni} with the most significant track in error; andcorrecting the erroneous tracks in accordance with said error vectors. .Iaddend..Iadd. 56. The method defined in claim 55, wherein i represents the position of the most significant track in error and j represents the position of the least significant track in error wherein the term by which combined error and parity vectors are divided is
1+B.sup.(-i-j). .Iaddend..Iadd. 57. The methd defined in claim 56, further including the step of detecting the presence of three or more tracks in error and preventing the correction of any of said tracks. .Iaddend..Iadd. 58. The method defined in claim 57, wherein said error vectors each comprise at least n bits, which bits are sequentially compared with corresponding bits in a given track of received data. .Iaddend. Description REFERENCE TO OTHER .[.PATENTS.]. .Iadd.PATENT DOCUMENTS .Iaddend. This is a continuation-in-part of Ser. No. 306,975, filed Nov. 15, 1972, now abandoned. Hinz, Jr. U.S. Pat. No. 3,639,900 shows using pointers for error correction purpose and a readback system which may employ the present invention. .Iadd. U.S. Pat. No. 3,508,194 shows construction of a modulo two adder usable in the present invention. .Iaddend. This invention relates to an error correction system for a multichannel parallel information handling system and, more particularly, to plural channel error correction using signal quality pointers and correcting signals from fewer than such plurality of channels without such quality pointers. In data handling systems, information is encoded for error detection and correction purposes by adding redundant bits to the data message in such a way that the total message can be decoded with an economical apparatus to faithfully supply the original information even when plural first errors occur in such message. Parallel data arrangements, that is, arrangements where the information is contained in parallel bytes arranged within a block of data, are used in computers and are well known, especially in multichannel recording apparatus. U.S. Pat. No. 3,629,824, filed Feb. 12, 1970, discloses encoding and decoding apparatus in which the redundant or check bits are associated with the data in a cross-byte or cross-track direction. This patent sets forth a code capable of correcting one or more errors within one byte of data having a given number of bits. The data is divided into a plurality of fixed-sized signal sets each consisting of k bytes of data (each byte having b bits), plus two check bytes, each of b bits. The decoder recovers the data without error when not more than a single byte of the received message is in error no matter how many bits may be in error in the single byte. Co-pending U.S. application, Ser. No. 99,490, filed Dec. 18, 1970, and now U.S. Pat. No. 3,697,948, utilizes the above-identified code, but extends the capabilities thereof by combining therewith pointer signals which extend the error correcting capability of the arrangement to two bytes in error regardless of the number of bits in error in each byte. These systems require two channels for the two additional check bytes needed for error correction, respectively. As the density of the information along the tracks or channels has increased, a faster, more reliable, simpler, but powerful, error correcting scheme is required which utilizes only one additional track for check bits. In one-half inch magnetic tape systems, it is highly desirable that tape be readable in both directions of transport. Usually, the tape is recorded only when transported in a first direction, arbitrarily defined as forward. A tape recorder should read in the forward and backward directions. When this fact is coupled with error detection and correction requirements, it is apparent that error codes should be operable for both directions of data transfer. Since the bit sequences are unalike in such transfers, many error detection and correction schemes require the data be accumulated before performing the error functions. For controlling costs and enhancing data throughput, it is desirable to perform error encoding and syndrome generation during readback on a serial basis--that is, perform calculations concurrently with data transfer rather than wait for all data transfers to be completed. Accordingly, it is a main object of the present invention to provide error correcting systems and methods in which information signals are encoded in the cross-track (vertical) direction as well as the track-length (horizontal) direction and decoded so that the error correction is selectively applied along a selected track or channel. It is another object of the present invention to provide plural channel error correction which requires only one channel for check bits in a parallel multichannel information system. It is a further object of the present invention to provide error correction which utilizes a minimum redundancy to obtain correction of signals from plural tracks in error with signal quality pointers and at least one such track in error without such signal quality pointers. It is a main feature to provide orthogonally symmetrical error detection and correction. Another feature is to employ plural independent error codes with interaction means simultaneously using both code redundancies to effect one error correction action with a capability equal to the sum of the error correction code individual capabilities. Briefly, the invention contemplates error correcting apparatus for simultaneously correcting plural channels in error in a parallel channel information system wherein the information signals are encoded for error correction purposes in a cross channel (byte or vertical) direction as well as in the channel or horizontal direction. The encoded information signals are decoded so as to provide error correction in the channel direction in any single channel in error or in a number of channels in error which are indicated as being in error. Error correction apparatus is constructed in accordance with a matrix for both vertical and horizontal directions having a selected orthogonal symmetry. This symmetry is chosen to enable check bit generation along one dimension and correction along an orthogonal dimension. The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawing. FIG. 1 is a schematic representation showing eight data channels or tracks and a parity track, such as found on one-half inch tape. FIG. 2 is a schematic topological representation of the data format on the tracks in the system showing the check bits along the vertical or cross-track direction and the vertical parity bits on the separate independent track or channel. FIG. 3 is a schematic representation of the layout of the bytes of data in the cross-track direction for a 9-track tape system. FIG. 4 shows the parity check matrix H for encoding of the data in the cross-track direction. FIG. 5 is a schematic representation of the 9-track system showing the data arranged in the longitudinal or track-length direction. FIG. 6 shows the parity check matrix H for decoding and error correction in the track-length direction. FIG. 7 is a block diagram of the encoder. FIG. 8 is a schematic representation showing the shift register mechanization for the encoding of the information. FIG. 9 is a schematic diagram of the byte parity generator shown in block form in FIG. 7. FIG. 10 is a schematic block diagram of the decoder and error corrector. FIG. 11 is a schematic block diagram showing a feedback shift register for decoding. FIG. 11a is a schematic block diagram showing the T FIG. 12 is a schematic block diagram showing the shift register SR3 for decoding. FIG. 13 is a schematic block diagram showing the details of the N indicator shown in FIG. 10. FIG. 14 is a diagram showing the layout of the FIGS. 14a, 14b, and 14c which form the error track parameters generator. FIG. 14a is a schematic block diagram showing the details of the generation of the I indicators. FIG. 14b is a schematic block diagram showing the i parameter as a binary number. FIG. 14c is a schematic block diagram showing the generation of the j-i indicators. FIG. 15 is a schematic diagram showing the error pattern generator of FIG. 10. FIG. 15a is a schematic block diagram of the M FIG. 16 is a schematic block diagram of the ring counter shown in block form in FIG. 10. FIG. 17 is a schematic block diagram of the code pointer generator shown in block form in FIG. 10. FIG. 18 is a schematic block diagram showing the error corrector block of FIG. 10 in more detail. In operation, information in the system is fed in parallel form to an error correction residue encoder wherein check and parity bits are sequentially generated for information signal sets referred to as bytes. These parity and check bit signals are supplied with the information signals such that the information signals can be error corrected. The present invention, via its orthogonal symmetry, enables calculation of check bits and syndromes using signals grouped in a so-called vertical direction and employs signals derived from such calculated signals to correct signals aligned in an orthogonal or so-called horizontal dimension. The invention also permits so-called backward error correction capability. The standard way of recording binary data on one-half inch tapes is a 9-track format diagrammatically shown in FIG. 1. One of the tracks P or track 8 is reserved to record "parity" over the other eight tracks, one parity bit for one byte recorded with one bit in each of the eight tracks. Such parity bit is known as the vertical redundancy check (VRC) bit as set forth in U.S. Pats. Nos. 3,508,194, 3,508,195, and 3,508,196. Each byte consisting of eight information bits and the parity bit is simultaneously recorded with one bit in each of the nine tracks and is read back and reassembled as bytes in accordance with Floros U.S. Pat. No. Re. 25,527. This data format has evolved over many years of wide use of magnetic record tapes. To correct one track in error, the so-called CRC system referred to above points to the track in error to enable error correction based on parity. This system only allowed correction of one track in one block of recorded signals. The present invention enables correction of all tracks provided no more than two tracks are in error at a given instant. Modifications of the invention may alter the number of correctable tracks in error. In designing new products, compatibility with the existing recorded tapes is one of the prime considerations in order that the tapes recorded on different machines can be freely interchanged. Bit density in the direction of motion of the tape in much greater than track density. Because of self-clocking aspects in reproducing recorded signals, one error-causing phenomenon results in the following signals in the same track to be in error, referred to as a burst of errors. Such errors are mainly caused by defects in the magnetic media and separation of tape from transducer resulting in a loss of synchronization or skew information in the readback circuits. The erroneous tracks are often indicated by loss of signals in the read amplifiers or change in phase between a clocking signal and the readback signal. This invention enables correction of these types of errors simultaneously occurring in plural channels. In the invention, the error correcting signal set topology for recorded or transmitted code words is in the geometric or time form of a block or rectangle conceptually with two orthogonal sides having check and parity bits, as shown in FIG. 2. The byte vectors are enumerated from C, the check byte, through B The track correction is obtained by correcting the clusters of errors along the tracks in error. It is well known that the error correcting codes for symbols from GF(2 Because of orthogonal symmetry, this invention avoids this restriction of symbols in GF(2 It will be appreciated by those skilled in the art that this invention can be applied to diverse information signal handling systems of varying capacities. The invention will, therefore, be described in terms of the known 9-track magnetic tape recording system, such as taught by Hinz, Jr., supra. The present invention employs orthogonal symmetry in check bit residue generation and utilization for enabling generation of such check bits by sequentially analyzing each byte of data, one bit to a channel, and then correcting several bits along each channel using the byte-generated residue. To accomplish this end, the underlying parity check matrices for the byte-oriented or vertical residue generation establish an identical data-bit-to-check-bit relationship as that established when the check bits are calculated either in the horizontal or track direction. The identicalness required in such data-bit-to-check-bit relationship is described later with joint reference to FIGS. 4 and 6. Such identicalness requires an orthogonally symmetrical operation, both in error check bit generation and utilization apparatus. The term orthogonal symmetry pertains to the information and check bits independent of the vertical parity bits. As will become apparent, such orthogonal symmetry enables the check bits generated based upon the byte information signals B
T
T In the above two equations, B's are the information bytes across tracks 0-7; C is the check bit byte across tracks 0-7; Z's are the signals along tracks 0-7, respectively, within a given signal set, viz, in track 0, bit 0, of B The above two equations show that the serial matrix multiplication and modulo 2's summation of the terms equal the modulo 2 sums of matrix multiplication using the same matrices but multiplying with the information signals and single check bit signal value along the indicated tracks. With this equality, check byte C is generated based upon the bytes B In a best mode, the number of bytes B In a preferred and best mode form, the code words of the code of the present invention, mathematically, have rectangular or block format of vertical dimension n Remembering the orthogonal symmetry concept and that an additional channel is used for an ancillary parity check field, such n The check bits are orthogonally located in the message block rectangle (nothing to do with the orthogonal symmetry referred to above). In 9-track tape, the parity track is along the center of the tape; hence, the vertical check bits are central of dimension n The data format for a preferred form of the code of the present invention, herein identified as an optimal rectangular code (ORC), for 9-track tapes is diagrammatically shown in FIG. 3. Each independent error correcting signal set has seven bytes of information respectively and arbitrarily denoted by B
P(0)=C(0)⊕C(1) . . . ⊕C(7) (1-E) and
P(i)=B For odd parity:
P(0)=C(0)⊕C(1)⊕ . . . ⊕C(7) (1-0) and
P(i)=B For odd parity:
P(0)=C(0)⊕C(1)⊕ . . . ⊕C(7) (1-0) and
P(i)=B for
i=1,2 . . . 7 where ⊕ denotes modulo 2 sum; P(0), P(i) is the modulo 2 sum; and P(0) and P(i) is the complement of the modulo 2 sum. The check byte C is computed from the information bytes B
C=TB where T is the companion matrix of an irreducible binary polynominal g(x) of degree 8 and T
g(x)=g where:
g and g The generalized companion matrix T of the polynomial g(x) degree 8 is defined as: ##EQU2## The check byte C can be generated by means of a feedback shift register, Exclusive-OR circuit array, programmed machine (preferably microcoded), and the like. A shift register implementation is described as the most economical for a given data rate. For lower data rates, a programmed machine is more economical, while for higher data rates, Exclusive-OR circuit arrays may be required. The above equations define the rules for encoding the message. These rules can be specified by the conventional means of a parity check matrix H. For this purpose, we characterize the matrices T Let α be the element of the GF(2 Matrices for an error correction apparatus consist of α column vectors; T For one code exhibiting orthogonal symmetry, as later explained, one set of α The selected α column vectors constituting the matrices T are:
T
T
T
T
T
T
T
T hence, yielding eight unique matrices as shown in FIGS. 4 and 6. The column vectors α The above-selected column vectors α
T
T
T
T
T
T
T
T where α In general, to put check byte C (first) in byte position "k"(k=0-7), the matrix T The above α-column-vector-to-matrix-T relationships yield a separate and independent EXCLUSIVE-OR equation for each of the eight check bits in check byte C. Such selection reduces hardware complexity, hence, is desirable from a cost view. Such separate and independent equations are not necessary. Check byte C can be associated with the data bits by other than the identity matrix I An example of such an arrangement using α
______________________________________Matrix α's Byte______________________________________T Since α
T=[α In (4a ), α is the leftmost column vector, α
T α Using equations (5) and (6a), we can write:
T
=[Tα and in general for any positive integer i:
T If cycle length n of a cyclic subgroup is the exponent of the polynomial g(x), then T
T One parity check matrix H can be constructed using equations (1), (2), (3a), and (7) and as presented in FIG. 4. It will be appreciated that α Before showing identicalness (orthogonal symmetry) between the matrices of FIGS. 4 and 6, error modes and data manipulations for error control are discussed. The most common errors in tapes are burst errors in a given track. A burst error affects every track byte in a fixed bit position i where i is the lowest number of the track in error, 0-7. The parity track P is not included in the matrix multiplication. The respective collections of eight bits, C(i), B
[I where I
Z and:
T where 0 is an 8-digit column-vector with all zeroes. FIGS. 4 and 6 show two parity check matrices for the FIG. 2 illustrated signal set. The FIG. 4 check matrix is byte oriented, while the FIG. 6 check matrix is track oriented. It will be shown that for each data bit in B Take any data bit from FIG. 2 and examine same in both FIGS. 4 and 6; the identicalness of its relationship to the error correcting redundancy becomes apparent. Bit 54 (B The above orthogonally symmetrical relationship is also established by noting the relationship of the α column vectors in FIGS. 4 and 6. In FIG. 4, byte B A corollary is that each bit in byte C is related to a set of bits in an identical manner by both check matrices. Take bit 2C. In FIG. 4, bit C(2) relates to α
C(2)=B noting that bit 0 is in Z
C(2)=11⊕02⊕73⊕64⊕55⊕46⊕37⊕76⊕67⊕77 For g(x)=1+x In FIG. 6, C(2) is aligned with T
C(2)=Z Since C is byte 0, the first bit in each track Z is in B
C(2)=02⊕11⊕37⊕46⊕55⊕64⊕73⊕67⊕76⊕77. Since, in modulo 2 addition, the order of terms does not alter the answer, the check-bit-to-data-bit relationships are orthogonally symmetrical for check bit C(2). Such symmetry for C(0) is shown in FIG. 2 as the hatched bit signals; i.e.,:
C(0)=0C⊕71⊕62⊕53⊕44⊕35⊕26⊕17⊕74⊕65⊕56⊕47⊕75⊕66. In a similar manner, C(1) symmetry is shown below using the FIG. 3 geometry and the corresponding α column vectors.
______________________________________-- 01 -- -- -- -- -- --* -- -- -- -- -- -- ---- -- -- -- -- -- -- 27-- -- -- -- -- -- 36 ---- -- -- -- -- 45 -- ---- -- -- -- 54 -- -- 57-- -- -- 63 -- -- 66 67-- -- 72 -- -- 75 76 77______________________________________ where * is the check bit. The line of symmetry is between upper left and lower right corners of the array, also as shown in FIG. 2. Using the same geometry, such symmetry is shown for all check bits.
______________________________________For C(2): -- -- 02 -- -- -- -- -- -- 11 -- -- -- -- -- -- * -- -- -- -- -- -- -- -- -- -- -- -- -- -- 37 -- -- -- -- -- -- 46 -- -- -- -- -- -- 55 -- -- -- -- -- -- 64 -- -- 67 -- -- -- 73 -- -- 76 77For C(3): -- -- -- 03 -- -- -- -- -- -- 12 -- -- -- -- 17 -- 21 -- -- -- -- 26 -- * -- -- -- -- 35 -- -- -- -- -- -- 44 -- -- -- -- -- -- 53 -- -- 57 -- -- 62 -- -- -- 66 67 -- 71 -- -- -- 75 76 --For C(4): -- -- -- -- 04 -- -- -- -- -- -- 13 -- -- -- 17 -- -- 22 -- -- -- 26 16 -- 31 -- -- -- 35 36 -- * -- -- -- 44 45 -- 47 -- -- -- 53 54 -- 56 57 -- -- 62 63 -- 65 66 -- -- 71 72 -- 74 75 -- --For C(5): -- -- -- -- -- 45 -- -- -- -- -- -- 34 -- -- 17 -- -- -- 23 -- -- 26 27 -- -- 32 -- -- 35 36 37 -- 41 -- -- 44 45 46 47 * -- -- 53 54 55 56 -- -- -- 62 63 64 65 -- -- -- 71 72 73 74 -- -- 77For C(6): -- -- -- -- -- -- 06 -- -- -- -- -- -- 15 -- -- -- -- -- -- 24 -- -- 27 -- -- -- 33 -- -- 36 37 -- -- 42 -- -- 45 46 47 -- 51 -- -- 54 55 56 57 * -- -- 63 64 65 66 -- -- -- 72 73 74 75 -- --For C(7): -- -- -- -- -- -- -- 07 -- -- -- -- -- -- 16 -- -- -- -- -- -- 25 -- -- -- -- -- -- 34 -- -- 37 -- -- -- 43 -- -- 46 47 -- -- 52 -- -- 55 56 57 -- 61 -- -- 64 65 66 67 * -- -- 73 74 75 76 --______________________________________ From the above charts, it is seen that each check bit * is in a diagonal line of bits mathematically orthogonal to the line of symmetry and that all data bits are either in such line or in parallel lines all to one side (below, as shown) of the line including the check bit. For C(0) the transverse diagonal is the single check bit. Examination of the above charts shows that shifting the matrices T Based upon the above discussion and FIGS. 4 and 6, the following two fundamental theorems are promulgated. Any error pattern in any one vector along the horizontal dimension (along a record track from the Z Proof A syndrome generated from any single track error pattern is a 16-digit binary vector formed by the linear combination of the columns of the H matrix (FIG. 6) corresponding to the digit positions in error. Let S
S if vector Z Equation (10) can be written in terms of the algebra of GF(2
for i=0-7: S
for i=8: S The theorem also shows that track i is not ambiguous by showing that for any track j not in error, i is unique. Let j denote a horizontal vector not in error (track not in error). That is, for j≠i, we have 0≠α Theorem 2: Any error patterns in any identified two vectors along the horizontal dimension (tracks) are correctable (note that tracks in error are detected or identified by operation of pointer apparatus independent the error correction apparatus). The two tracks in error are separately indicated, for example, by pointers in accordance with Hinz, Jr., supra. Such pointers indicate low-quality signal processing; hence, the probability of error is much greater than in those tracks without such pointers. Proof: Let e
for all cases: S
for j≠8: S
for j=8: S For j≠i, equations (11) and (12a) are independent equations in GF(2
for j≠8: e
j=8: e
for all cases: e The multiplication and inverse of the vectors are the field operations in GF(2 The coded message can be generated using any irreducible binary polynomial g(x). For the preferred tape embodiment, Table 1 gives the irreducible polynomials of degree 8 with their exponents. Choice of g(x) of degree 8 from this set could be arbitrary; however, for tape recorders, there is an advantage in choosing a self-reciprocal polynomial or one with a lower value of exponent. Such a choice facilitates error correction during backward read as desired for digital tape recorders. In Table 1, polynomial numbers 8 and 16 are self-reciprocal and have the lowest value of exponent. Reciprocal polynomial g(x)=x
Table 1______________________________________Irreducible Polynomials of Degree 8Polynomial Coefficients of the Polynomial ExponentNo. g The above irreducible polynomials, having an exponent value of 255 are primitive polynomials. When such primitive polynomials are selected, any one of the 255 α column vectors may be chosen for practicing the present invention. In the other nonprimitive polynomials, a number of α column vectors up to the exponent value may be used. a. Encoding (Generations of check bit and parity check residues)--From the prior theoretical description, check byte C is computed from the information bytes B Shift register 10 contains eight binary storage elements or stages (0) . . . (7), one for each data track 0-7, with appropriate feedback connection 24 and modulo 2 summing networks 26 intermediate the binary storage elements. Under a timing control signal, the shift register synchronously shifts the contents of one stage to the next stage while simultaneously receiving a new input and feeding back as explained for FIG. 8. Shift register devices of this type are widely known and, given the feedback connections made in accordance with polynomial g(x), are easily constructed from available logic hardware in many different ways. Referring to FIG. 8, input data bytes B g(x)=1+g
TB the check byte C. C is then gated out. The byte or vertical parity of B Check byte C contains the check bits resulting from implementing equation (3a) and is respectively associated with the information or data signals in a particular track or channel. Also, the parity bit signals for the cross-track or vertical information signals are located in a separate track P. b. Decoding (Error syndrome generation)--Let Z
S
S Calculation of S According to this invention, S
S S
S wherein the negative exponents of each matrix T indicate backward shifting. The feedback connections are made according to g(x) Table 1); however, the shifting operation is backwards and corresponds to multiplying the shift register content vector by the matrix T In a practical embodiment, equation (14b) represents operation in a so-called forward direction wherein the byte order is B S c. Generation of Error Patterns (e The quality pointer signals are derived from the system in which the error correction is taking place. Of course, there are various means of generating "pointer" signals such as is set forth in Hinz, Jr., supra. In this application, the quality of the record/readback operations on a real-time basis is used as quality pointers to possible error conditions. The error correction apparatus also generates error pointers, hereinafter termed "code pointers". The syndromes S
S for i≠j≠8:
S for j=8; j=i:
S S
e where: for j≠i≠8:
M for j=i or j=8:
M wherein I Equation (15) can be realized in the following manner: T When only one track is in error (the case with i=j and e
e This is done by counting the number of shifting operations (matrix multiplications) of SR2 (with S d. Correction of Tracks in Error--Using the error pattern e
Z
Z Referring to FIG. 7, there is shown a block diagram of an encoder for the system. We will describe encoding for one set of input data bytes B To sequence encoder operation for each set of input data bytes, at the start time of the encoder, t The byte parity generator 14 is shown in FIG. 9. B After the message has been encoded and recorded, reproduced signals from the recorded tape (not shown) are transmitted in 9-bit record byte serial form to decoder (FIG. 10). The readback byte sequence can be forward B The received message bytes B In response to the quality pointer signals, N indicator 74 generates signals N The FIG. 10 decoder first computes the syndromes S Binary control counter 60 zero count indicates all bytes C . . . B For an error-free condition P=P yielding S The case of less than two tracks in error indicated by the pointers Q is processed as follows. In this case, the N indicator produces the N
e Track i is identified by shifting S Of course, the presence of the N For two-track correction, counter 60 is utilized while ring counter 70 is utilized when there is only one or no track in error. The N indicator 74 generates the signals N The error pattern generator 45, on receiving S The error corrector 42 utilizes the error pattern e It will be appreciated that in the case of only one track error or no tracks in error, the corresponding values of e A better understanding of the operation of the error correction system may be obtained from the details of the various circuits forming the decoding system. The frame buffer and data distributor 40 can be of any known form capable of deskewing and distributing the information as required. It will be appreciated that the information input to the frame buffer and distributor 40 is in the form of 8-bit bytes each with a parity bit. The cross-track information is distributed to the shift registers SR3 and SR2 in parallel byte form as shown in FIG. 10 with the check byte first. A most basic storage and deskewing means would be a series of registers, one for each byte of information. The registers could be readable in the reverse direction as well as a direction orthogonal to the read-in direction to obtain the Z The shift register SR2 is shown in detail in FIG. 11. The information byte or check byte is shown as the input to a T
g(x)=1+g If g
S The T The FIG. 11 illustrated circuit is usable for both read forward and read backward operations of a digital tape recorder. The upper connections, identical to and labeled SR1, provide operations in read forward (FWD). The FWD signal activates modulo 2 adders 26 to modulo 2 add the quantity B Generation of FWD and BKWD signals are from host CPU commands received by an I/O controller (not shown) respectively commanding read forward or backward. FIG. 12 shows the shift register SR3 of the decoder. The input bytes C, B FIG. 13 shows the N indicator circuit 74 which is capable of providing the control signals N FIG. 14 shows schematically the error track parameters generator 54 which generates the code pointers 1 identifying the first erroneous data track which is called the I Referring to FIG. 14a, there is shown the logic network connections for generating the I pointers I FIG. 14b has as input the I indicators generated in FIG. 14a. The circuit generates the i parameter as a b-bit binary number. The input combinations of the I indicators are determined according to columns in Table 2. The logic connections are determined in accordance with the 1's in the row in the columns of Table 2. For example, the column i(0) has a 1 in the 1, 3, 5, and 7 positions. Accordingly, the connections to the first OR circuit are the I
Table 2______________________________________Parameter I as a Binary Number i as Binary Numberi Indicated By: i(2) i(1) i(0)______________________________________0 I FIG. 14c shows a logic circuit diagram which generates the j-i values from the track pointers Q. This is accomplished by combining the Q pointers into pairs of inputs to separate AND circuits 80. The input paired arrangement of pointers has a first group of pairs separated by the value 1, while a second group of pairs is separated by the value 2. The third pair is separated by the value 3, the fourth pair by the value 4, etc. Each of these Q pointer pairs is fed to respective AND circuits 80 whose outputs form the input to appropriate OR circuits 82 to obtain the appropriate j-i value. The j-i=1 value is obtained from the first OR circuit 82a which has as inputs thereto the outputs from the first group of and circuits 80a which have the input pairs separated by one. Similarly, the other OR circuits 82b-82f have connections thereto based on similar properties. For example, the second OR circuit 82 has an output value j-i=2; while the third OR circuit 82c has a value j-i= 3, etc. A single input pair N FIG. 15 shows the error pattern generator 45 generating the second error in the two track erasure error and the e FIG. 15a shows the details of the M The connections of the various modulo 2 adder circuits 92 in the M Referring to FIG. 16, there is shown the details of the ring counter circuit 70 as shown in block form in FIG. 10. The ring counter 70 is shown having 0-8 stages with a feedback 94 from the eighth to the 0 stage. The output from each successive stage going to the next numerically higher state. The output from each of these stages is the corresponding count output r Referring to FIG. 18, there is shown the error corrector circuit 42 which produces the corrected data bytes Z
Z
Z It can be seen from these equations as shown in FIG. 10 that e As aforestated, magnetic tapes are read in both forward and backward directions. The error correction methods and apparatus of the present invention accommodate such requirements. When reading in the so-called forward direction, the decoder may be operated in the same mode as the encoder or backward shifted to save time. When readng the so-called backward direction, a backward shift with T Since the parity portion and orthogonally symmetrical portion are independent, in the event of catastrophic failures, two degraded modes of operation with correction are possible--one using parity only and a second using ORC only. For a single track correction without the parity track, an independently generated track pointer is required. The described apparatus for two-track correction is employed while forcing j=8; the single track in error i will be corrected as described for two-track correction (using an independent pointer). Broadly, without the parity (or other code) inputs, the error correction capability is reduced and separate track identification is required; but the orthogonal symmetry still enables correction along a track based upon cross-track byte calculations. The invention may also be practiced with nonbinary notation, i.e., ternary, decimal, hexadecimal, etc., with equal advantage. The parity vector P may be a Hamming code, Fire code, and the like, or even a residue based upon a different polynominal. While the invention has been particularly shown and described with reference to a preferred embomdiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. Patent Citations
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