|Publication number||USRE30917 E|
|Application number||US 06/104,270|
|Publication date||Apr 27, 1982|
|Filing date||Dec 17, 1979|
|Priority date||Jul 31, 1975|
|Also published as||CA1072674A, CA1072674A1, DE2634312A1, DE2634312C2, US4064524|
|Publication number||06104270, 104270, US RE30917 E, US RE30917E, US-E-RE30917, USRE30917 E, USRE30917E|
|Inventors||Yoshiaki Hagiwara, Hiroshi Yamazaki|
|Original Assignee||Sony Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Non-Patent Citations (2), Classifications (20)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates in general to charge coupled devices and in particular to a novel charge coupled device and information storage device for storing and sequentially transferring electronic signals in representative of information.
2. Description of the Prior Art
Charge coupled devices have been well known for storing and transferring charges in a storage medium by the use of appropriate potentials applied upon an insulating layer overlying one surface of a medium. For example, the article entitled "Charge Coupled Imaging: State of the Art" which appeared in Solid State Devices 1973, pages 83 through 107 disclose a number of charge coupled devices as well as charge coupled image sensors.
Prior art charge coupled devices have used a plurality of aligned gates overlying an insulating layer on a substrate and wherein three phase clock signals are respectively applied to the gates.
Other charge coupled devices have utilized semiconductors having a layer of insulating material, as for example, silicon dioxide which varies in thickness and upon which aligned pairs of gates are arranged so as to operate with two phase clock signals.
It has also been known to provide asymmetrical doping under the gates so as to obtain asymmetrical charge distribution in the device. However, the use of three phase clock pulses, varying thickness of the insulating layer under the gates and asymmetrical doping results in complicated and expensive devices and methods particularly for obtaining the varying thickness of the insulating layer and the asymmetrical doping are very difficult to perform.
The present invention comprises a novel charge coupled device capable of operating with two phase clock signals and wherein channel stoppers are provided on opposite sides of the gates in the semiconductor material with restricted openings between adjacent storage areas under the gates so as to provide asymmetrical charge distribution in the charge transfer device.
In a specific application as an image sensor light sensing elements are provided adjacent storage elements in charge transfer devices with channel stoppers arranged so as to prevent charges from passing from a light sensor element to an adjacent light sensor element but which allows charges to flow from a particular light sensor element to its associated storage element and wherein said channel stoppers further are formed so as to provide restricted areas between adjacent storage areas to thus provide asymmetrical charge distribution and charge transfer in a unilateral direction through the storage device upon the application of clock signals.
A main object of the invention is to provide a two phase clock type charge transfer device which is free from the drawbacks of the two phase and three phase clock type devices of the prior art.
Another object of this invention is to provide an interline transfer system for a solid state area imaging device using a novel two phase clock type charge transfer device system.
In the invention a channel stopper region formed in a solid state area imaging device is used to form an asymmetrical potential well. Also, in this invention, a potential well can be easily formed without changing the thickness of the insulated oxide film over the substrate and the desired asymmetrical potential well can be formed by a channel stopper region having a predetermined shape.
Other objects, features and advantages of the invention will be readily apparent from the following description of certain preferred embodiments thereof taken in conjunction with the accompanying drawings although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure and in which:
FIG. 1 illustrates a prior art three phase charge coupled device;
FIG. 2 illustrates a prior art two phase charge coupled device;
FIG. 3 is a top plan view of a solid state imaging device;
FIG. 4 is an enlarged plan view illustrating the solid state imaging area of the invention;
FIG. 5 is a cross-sectional view taken on line A--A of FIG. 4;
FIG. 6A is a cross-sectional view taken on lines c or c' from FIG. 4;
FIG. 6B illustrates the potentials in FIG. 6A;
FIG. 7A is a cross-sectional view taken on line b or b';
FIG. 7B illustrates the potentials in FIG. 7A;
FIG. 8A is a plan view illustrating a portion of FIG. 4;
FIG. 8B is a view illustrating the potential on a line taken on section line B--B of FIG. 8A;
FIG. 9 is a partial sectional view illustrating a modification of the invention;
FIG. 10 is a partial sectional view illustrating a modification of the invention; and
FIG. 11 is a top plan view illustrating a charge transfer device according to the invention.
Prior art charge coupled devices have been either three phase or two phase clock types. FIG. 1 illustrates a prior art three phase clock type transfer device which comprises a substrate 5 made of, for example, silicon upon which a dielectric layer 6 made of silicon dioxide or some similar substance is deposited and a plurality of gate electrodes 7 are formed on the silicon dioxide layer 6 and are arranged in a charge transfer direction to form a transfer device. Every third gate electrode 7 is connected together to provide three sets of electrodes to which are applied three phase clock voltages φ1, φ2 and φ3 so as to form potential wells having different depths in the substrate under adjacent gate electrodes so that electrical charges being stored can be transferred unilaterally through the device. In such a three phase clock type charge transfer device, however, it is a drawback because the three phase drive is troublesome and the electrical conductive layers for supplying feed voltage to the gates will have a complicated pattern and in an image sensing device the number of picture elements per unit area cannot be increased when forming a solid state area imaging device.
FIG. 2 illustrates another example of charge coupled devices of the prior art utilizing two phase clock drive in which the elements similar to those in FIG. 1 are shown by the same reference numerals but wherein the dielectric layer 6 is made to have differing thicknesses under the gates 7 so that each gate has a first portion which is over a relatively thin layer of silicon dioxide and second portions which are over relatively thick portions of silicon dioxide. Such structures allow two phase clock drive which can be applied to alternate electrodes to transfer charge in a unilateral direction because potential wells which are asymmetrical relative to the charge transfer direction are formed in the neighborhood of the substrate surface under each electrode 7 due to the varying thickness of the dielectric 6. With such an arrangement, when two phase clock voltages φ1 and φ2 are applied, electrical charges will be transferred in one direction. The two phase clock type charge transfer device described is suitable for use in interline transfer system solid state imaging devices. Conventional two phase clock type CTD in which the thickness of the dielectric under each electric is made different at the front and rear portions relative to the charge transfer direction are very difficult to fabricate. Also, other prior art devices wherein the impurity concentration of the substrate surface under each electrode is made to vary between the front and rear edges are known, however, such devices are also very difficult to construct. Furthermore, the miniaturization of such devices is very difficlt due to the varying thicknesses of the dielectric 6 and/or the variation in the doping concentration.
FIG. 3 illustrates a solid state area imaging device using CTD, for example, using interline transfer system wherein there are disposed in a semiconductor substrate a plurality of island-like light sensing elements 1 which serve as the picture elements and are arranged as shown in FIG. 3. A vertical shift register having CTD construction is disposed at one side of each column of the light sensing elements 1 and a common horizontal shift register 3 also having CTD construction is provided at one end of each of the shift registers 2 so as to receive their outputs. The vertical shift registers 2 have transfer portions corresponding to the respective light sensing elements 1 and signal charges corresponding to the amount of light impinging upon each of the elements 1 are transferred to corresponding transfer portions of the vertical shift registers 2 by a charge transfer device construction illustrated in dotted line by 4. The transfer charges are shifted to the horizontal shift register 3 by the vertical shift registers 2 and the signal is successively derived from an output terminal t of the horizontal shift register 3. These light sensing elements 1, the shift registers 2 and 3 are formed on a common semiconductor substrate and the portions between adjacent sensing elements 1 and the portions between the light sensing elements and the shift registers which are to be separated from each other are formed with channel stopper regions which are heavily doped with impurities so that they are isolated electrically from each other. The prior art solid state area imaging devices utilize CTD construction as discussed in the prior art above and have the same defects as such devices.
FIGS. 4 and 5 illustrate one example of an interline transfer system utilizing a solid state area imaging device according to the invention. A silicon substrate 10 of one conductivity type, for example N-type which has an impurity concentration of about 1015 atoms/cm3 has provided on its main surface 10a a plurality of light sensing elements 11 arranged in rows and columns so as to provide a light sensing matrix. A plurality of vertical shift registers 13 are each respectively associated with a column of light sensing elements and are provided with transfer regions 12 each of which corresponds to a light sensing element on one side thereof as shown.
Each light sensing element 11 is formed of a region 14 having a conductivity type different from that of the substrate 10 and might, for example, be P-type and have an impurity concentration of about 1017 to 1018 atoms/cm3. The regions 14 can be formed by the same diffusion process during which the source and drain regions of an output MOS transistor (not shown) is formed and which is provided at the output for example of the horizontal shift register of the solid state imaging device.
In the substrate 10 are also provided channel stopper regions 15 which may contain N-type impurity concentration in the order of 1018 atoms/cm3 which concentration is sufficiently higher than that of the substrate and which can be provided from the surface 10a by ion injection methods, selective diffusion methods or similar processes. The channel stopper regions 15 are formed into a pattern such that they surround the peripheries of the respective light sensing elements and shift registers 13 except for portions between each light sensing element and its associated transfer region 12 of the shift register 13 as well as between adjacent transfer regions 12 of each shift register 13. In the example illustrated in FIG. 4 for example projecting portions 15a of the channel stopper region 15 project toward a corresponding projecting portion 15a between each light sensing element and its associated transfer region 12 so that the light sensng element 11 will not lose its electrical charge by leakage. In the example illustrated in FIG. 4, it is to be noted that the portions 15a extend toward each other from opposite sides of the light sensing element 11 but it is to be realized that a single projecting portion 15a can extend substantially toward the other side of the channel stopper and only a single projection need be used.
Additionally, second projecting portions 15b are provided which extend from each channel stopper region 15 and project between adjacent transfer regions 12 in each shift register 13 to form therebetween areas of reduced cross-section 16. In the example illustrated in FIG. 4, the portions 15b are formed at both sides of the transfer region and are arranged in the direction of each shift register 13 to form the reduced area portion 16 between opposite projection parts 15b, respectively. However, it is to be realized that various patterns can be provided so as to form the projection portions 15b at one side thereof of each of the regions 12, for example.
As shown in FIG. 5, a dielectric layer such as silicon dioxide 17 is formed on the surface 10a of the substrate 10 and windows 18 can be formed through the dielectric layer 17 and the light sensing element 11 can be formed so as to contact the P-type region 14. A plurality of transfer electrodes 19 (19a, 19b, 19c . . . ) are deposited over the dielectric layer 17 and over the transfer regions 12 of the respective shift registers 13 on each row. Each of the electrodes 19a, 19b, 19c . . . is deposited so as to extend over each transfer region aligned in a single horizontal row as shown in FIG. 4 and covers the transfer regions 12 and the regions of reduced areas 16 of the transfer region 12 located at its front edge with respect to the charge transfer direction "a". The electrodes 19 do not cover the windows 18 of the light sensing elements 11.
With the above described construction, when light impinges upon the light sensing element 11 (the P-type region 14) photoelectrons are generated depending on the amount of light and the electrons will escape into the channel stopper region 15 or substra te 10 so that a positive hole will be stored in the region 14. However, when electrical charges (positive holes) stored therein exceed a predetermined amount, the excess charges will escape into the region of the substrate 10. On the other hand, the electrical charges (positive holes) stored in the regions 14 will be transferred to the respective transfer regions 12 of each shift registers 13 which are formed corresponding to and adjacent to the light sensing elements 11. In other words, when the electrode 19 has applied thereto a predetermined transfer voltage, for example, -15 volts, the transfer region 12 will have a potential well which is deeper than that of the region 14 of the light sensing element and the electrical charges (positive holes) stored in the region 14 will be transferred to the transfer region 12.
The alternate electrodes 19a, 19c . . . and 19b and 19d . . . will be respectively combined to form two sets of electrodes to which are then applied two phase clock voltages φ1 and φ2. The voltage of the clock pulses φ1 and φ2 will be selected to be lower than the above mentioned transfer voltage of -15 volts which is transferred from the light sensing element 11 to the transfer region 12 and may be for example, -10 volts. FIGS. 6A and 7A are cross-sectional views respectively taken on chain lines c or c' and b or b' in FIG. 4. Thus, FIG. 6A is a cross-sectional view through a wide portion of the transfer region 12 and FIG. 7A is a cross-sectional view through the restricted portion 16. FIGS. 6B and 7B are views showing the surface potentials at the respective sections during a condition when the electrodes 19b, 19d . . . have applied thereto a clock voltage pulse φ2. In FIGS. 6B and 7B full lines illustrate the potentials in the region 12 and the restricted portion 16 respectively under the electrode 19a and the broken lines illustrated the potentials in the region 12 and restricted portion 16 respectively under the electrode 19b to which is applied the clock voltage pulse φ2. It will be apparent from these Figures that where the distance between the channel stoppers 15 is large will have a wider potential well than the restricted portion or contracted portion 16 form between adjacent transfer regions 12 between each of the shift registers 13 which will have a shallow potential well due to the influence of the potential of the channel stopper region 15. Even at the restricted or contracted portion 16, however, the potential well depths will differ as the clock voltage is applied are not applied as is apparent from the comparison between the full line and broken lines in FIG. 7B. Thus, the surface potential distribution of the regions 12 along their charge transfer direction will be changed at the front and rear sides in the transfer direction of the region 12 and will become asymmetrical.
FIG. 8A is a partial plan view of the shift register 13 and wherein the orientation is rotated 90° relative to FIG. 4. FIG. 8B is a view illustrating the surface potential on the section line B--B which corresponds to the chain line d in FIG. 4. In this example, the set of electrodes 19b, 19d has applied thereto the clock voltage pulse φ2. It is obvious that the potential at the substrate surface under the electrodes 19b, 19d . . . to which the clock voltage is applied is lower than that under the electrodes 19a, 19c . . . but the surface potential of the restricted or contracted portion 16 under the respective electrodes 19 are higher by Δa and Δb than those of the regions 12 under the corresponding electrodes 19. Therefore, each region 12 under the electrodes 19a, 19c . . . will be provided with a potential barrier having a height of Δa at its front edge with respect to the charge transfer direction and hence such an asymmetrical potential well will cause electrical charges to be transferred in a single direction that is, from each transfer region 12 under the electrode 19a toward the transfer region 12 under the electrode 19b.
As has been described above, according to the invention the asymmetrical potential well relative to the charge transfer direction is formed by the projecting portions 15b of the channel stopper region 15. Therefore, it is not necessary to vary the thickness of the dielectric layer in a step wise manner under each electrode or to change the concentration of the substrate surface as is done with prior art devices such as illustrated in FIG. 2. In other words, the two phase clock CTD of the present invention can be constructed in a simple manner without increasing the number of fabrication process steps over those of the prior art.
With the above construction, the transfer between adjacent transfer regions 12 in the shift register 13 can be accomplished with the clock voltage pulses φ1 and φ2 which are smaller than the voltage for shifting electrical charges from the light sensing element 11 to the corresponding transfer region 12.
If the width of a restricted or contracted portion 26 formed by the projecting areas 15a of the channel stopper 15 which are projected toward the light sensing element 11 and the corresponding region 12 is taken as Ws and the width of the contracted part 16 is taken as Wt the relationship therebetween can be suitably selected such that Ws is exactly equal to 5 μm and Wt is exactly equal to 6 μm. With the above mentioned relationship while the transfer is being carried out in the shift register 13 the electrical charges will be prevented from flowing from the light sensing element 11 into the corresponding transfer region 12 of the shift register 13 or alternatively from the region 12 into the region 14 of the light sensing element 11. This is because of the voltages mentioned above of -10 volts and -15 volts are used as the transfer voltages.
When the light sensing element 11 is composed of a region 14 of P-type which is different from the conductivity type of the substrate region as mentioned above, electrical charges which are in excess and are stored therein will flow into the substrate so that an overflow drain is not necessary to be specifically provided and thus a space saving results.
In the above described embodiments, the invention is applied to a vertical shift register of the interline transfer system solid state area imaging device. However, the invention can be applied to the horizontal shift register (output shift register) and also to any other type of solid state area imaging device or other CTD.
Furthermore, the invention has been described primarily in a case where the invention is applied to a surface CTD but it can also be applied to a buried type CTD. Such an example is illustrated in FIGS. 9 and 10 wherein a semiconductor substrate 10 of one conductivity type for example, a N-type silicon substrate can be selectively formed with a region of other conductivity type or P-type facing its one surface 10a such that its transfer region 12 and a channel such as a reduced or contracted portion 16 between adjacent regions 12 should be formed and the N-type region of the substrate 10 itself can serve as a channel stopper region 15. In FIGS. 9 and 10 the elements corresponding to those shown in FIGS. 6A and 7A are indicated by the same reference numerals and their description will not be repeated.
FIG. 11 illustrates the principles of the invention by using channel stoppers having restricted portions in a charge coupled device.
A substrate 31 has formed therein channel stopper regions 16 and 17 which extend along opposite sides thereof and extending portions 18 and 19, 21 and 22, 23 and 24, 26 and 27, and 28 and 29 extend, respectively, from the channel stoppers 16 and 17 toward each other as shown. A dielectric layer 30 is formed over the surface of the substrate and channel stopper regions and electrodes 31 through 34 are formed over the dielectric layer 30 and are provided with input leads 36 through 39 as shown. Alternate leads 36 through 38 receive clock voltage pulses φ1 and the remaining alternate electrodes 37 and 39 receive clock voltage pulses φ2. The device in FIG. 11 receives charges at one end which are transferred through the device to the other end due to the asymmetrical potential wells caused by the restricted portions 19, 22, 24, and 27 and 18, 21, 23, and 26 for the same reason as described with respect to the embodiments illustrated above. Thus, as shown in FIG. 11 a novel charge coupled device can be provided without varying the thickness of the dielectric layer and are varying the impurity concentration of the device.
It is seen that this invention comprises a new and novel charge transfer device and although it has been described with respect to preferred embodiments it is not to be so limited as changes and modifications may be made therein which are within the full intended scope as defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
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|1||*||Sequin et al., Charge Transfer Devices, Academic Press, N.Y., (7/75), pp. 60, 61, 163, 164.|
|2||*||Walsh et al., "A New Charge-Coupled Area Imaging Device", Suppl. of Proc. CCD Applications Conf., San Diego, (9/73), 14 p.|
|U.S. Classification||257/233, 377/62, 257/248|
|International Classification||H04N5/3728, H04N5/341, H04N5/335, H01L29/768, H01L29/06, H01L29/10, H01L29/762, H01L27/148, H01L21/339|
|Cooperative Classification||H01L29/76866, H01L29/0646, H01L29/1062, H01L27/14831|
|European Classification||H01L29/06B3B, H01L29/768F, H01L27/148C, H01L29/10D3|