|Publication number||USRE33461 E|
|Application number||US 07/353,414|
|Publication date||Nov 27, 1990|
|Filing date||May 18, 1989|
|Priority date||Oct 16, 1985|
|Publication number||07353414, 353414, US RE33461 E, US RE33461E, US-E-RE33461, USRE33461 E, USRE33461E|
|Inventors||Katherine A. Splett, Steven H. Karban, Gerald L. Brown|
|Original Assignee||Unisys Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Referenced by (3), Classifications (11), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The generation of complex multiple timing cycles for digital logic systems commonly requires extensive complex logic circuitry. The verification of the operation of the timing circuitry in the past has imposed additional complexity on the design requirements of the system and has not provided a high level of confidence verification.
In digital logic systems, programmable read-only memory (PROM) is commonly used to store programs and data which are normally accessed by the host computer during operation. Additional PROM is often utilized for the storage and generation of the timing signals for the system. This PROM is not normally accessible by the host computer.
Also included in the system is a buffer and logic circuit. This is a group of buffers, combinational logic and sequential logic circuits which receive timing inputs from the PROM and timing and control inputs from other sources in the system. The buffer and logic circuit acts on these various inputs to produce a selected one of the several possible complex timing cycles.
This system consisting of the PROM and the buffer and logic circuit, has two modes of operation, a Normal mode for normal system operation and a Verify mode for timing cycle verification. In the Normal mode, a free running clock is coupled to an address counter, which successively selects a row in the PROM, which upon selection outputs the stored information in that row to the buffer and logic section. In this mode the address counter operates in a cyclic manner on a continuous basis, and the PROM is read out from the starting to the ending address of the PROM section which is employed for the particular timing mode that is selected. In the Verify mode, the free running clock is disconnected and replaced with a host computer controlled clock which is stepped pulse by pulse so that the address counter steps through the rows of the PROM at a rate controlled directly by the host computer.
Verification of programs stored in programmable read-only memory (PROM) is generally achieved through the use of diagnostic software routines which utilize a checksum operation. The present invention utilizes a PROM which has several sections, each of which stores timing information for a different selectable mode. In normal operation this timing information is only used to generate complex timing cycles, and it is not required to be accessible to the host computer. In order to verify correct operation of the timing circuits, the host computer, or an independent control section switches the timing circuit at a rate which allows the adder to provide a checksum for each row of the PROM, which is added to the checksum provided by all of the preceding rows. The digital checksum that is achieved is compared with a stored checksum which is known to be correct for the selected complex timing cycle. The present invention is thereby capable of providing diagnostic verification with a high level of confidence, for several different complex timing cycles that may be generated for timing the data processing system. For example, the timing generation may be used with a mass memory controller to ensure that the required timing cycles occur in the correct sequences and with the correct intervals.
The present invention is illustrated by reference to the FIGURE, which is a block diagram illustration of a system for diagnostic verification of multiple complex timing cycles.
A complex timing cycle generator is shown in the FIGURE. A control 12 which is a hardware unit provides a timing clock and various timing controls to the remainder of the timing cycle generator. When a Normal mode command is received on line 31 from the host computer by the control, it causes the output of the master clock 14 to be coupled to the timing clock output of control 12. Clock signals are coupled on the line 15 from clock 14 to an address counter 16 which operates over a range of addresses as determined by the timing control outputs of control 12. The counter may be reset and cycled over again, or it may be halted by command from the host processor on line 33 when a sufficient number of cycles of the timing generator have been completed.
A programmable read-only memory (PROM) 18 contains the timing information for at least two timing modes which may be generated by the timing generator. The address counter applies output bits, via lines 19, to PROM, the output of which is supplied as raw timing signals (16 bits) on the lines 20 to a buffer and logic circuit 22, in a sequential manner from the first accessed address to the last accessed address which is associated with the selected timing cycle. Thus m bits of the 32 output bits from the buffer and logic circuitry 22 are supplied on the lines 24, directly on the lines 25, and n bits are supplied via lines 27 and gates 40 as complex timing cycle bits to the timing lines 28. (n+m=32 in the disclosed embodiment).
During normal operation a HOST command on line 31 to the control causes the address counter 16 to cycle in a repeated pattern to create complex timing cycles of a selected pattern on the lines 20 until a HALT command is supplied to the control 12 on line 33. When the HOST command indicates that a different timing cycle pattern is to be implemented, a different section of the PROM 18 is selected by control 12. Repetitive cycling of the address counter will then cause a different group of stored bits in the PROM to be supplied on the timing lines 28.
The buffer and logic circuit 22 is employed to modify and convert the 16 bits of timing on the lines 20 coupled from the PROM to 32 bits of timing on the lines 24. The buffer and logic circuit 22 is ultimately under the control of the host computer, which directs it via control 12 in unison with the address counter 16 and PROM 18 to produce one of a plurality of timing cycle types.
During Verify mode operation of the timing generator, the control 12 will provide timing control signals from the lines 35 to the gates 42 as required to inhibit any error or status flag signals which otherwise might appear on the lines 23 during Normal mode operation and would interfere with the Verify routine. For example, inhibit signals may be provided on the lines 35 to prevent the error or status flags that are supplied on the line 23 via gates 42 to the lines 37 from affecting the diagnostic procedure; and also to disable some of the refined timing lines 28, via gates 40, to preclude the possibility of altering the data stored in the mass memory.
During the Verify mode procedure, the timing clock output from control 12 is operated in a stepped mode so that the address counter 16 steps through each of its possible selection address outputs at a rate which allows the adder 26 to sequentially receive and add the outputs on all of the lines 24 that are associated with one count of the address counter 16 before the next count is produced. The adder 26 then accumulates a checksum count for all of the accessed memory locations of the PROM for the selected timing cycle under the control of the address counter 16. The checksum output of the adder 26 on the line 39 is a test sum which is compared by the comparator 32 to a stored checksum supplied on line 41 from the checksum storage memory 30 for the timing cycle that is selected.
As noted in the drawing, control 12 supplies a timing control to the address counter 16, the buffer and logic circuitry 22, the adder 26, the comparator 32, and the checksum storage memory 30 so that these components have their appropriate elements selected in accordance with the timing cycle selected by the control 12. If the checksum stored and the sum in the adder 26 are found to be equal by the comparator 32 a Pass signal will be produced by the comparator on the line 43. If they are not equal a Fail comparison signal will be issued indicating the failure of the timing system for the particular cycle that was selected. Each of the individual timing cycles that are capable of being selected by the system may thus be individually verified by the timing generator and verifier of the disclosed embodiment.
In the disclosed embodiment sixteen output lines 20 are shown from the PROM 18. In addition, the lines 24 and 28 are shown as being greater in number to lines 20 but this is a function of the buffer and logic circuit 22. The buffer and logic circuit 22 may be implemented as required to produce various combinations of the signals from the lines 20 and from the timing control, so that it is not necessary for the number of output lines 24 to bear any fixed relationship to the number of input lines 20. The adder 26, comparator 32 and checksum storage 30 may be provided by dedicated hardware or by the host processor along with associated software.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5704033 *||Oct 6, 1995||Dec 30, 1997||Lg Semicon Co., Ltd.||Apparatus and method for testing a program memory for a one-chip microcomputer|
|US6728649||Feb 1, 2002||Apr 27, 2004||Adtran, Inc.||Method and apparatus for removing digital glitches|
|US6834356||Feb 15, 2000||Dec 21, 2004||International Business Machines Corporation||Functional clock generation controlled by JTAG extensions|
|U.S. Classification||714/736, 714/722, 714/814|
|International Classification||G06F11/10, G06F11/08, G06F1/04|
|Cooperative Classification||G06F1/04, G06F11/1004, G06F11/08|
|European Classification||G06F1/04, G06F11/08|
|Jul 23, 1991||FPAY||Fee payment|
Year of fee payment: 4
|Jun 26, 1995||FPAY||Fee payment|
Year of fee payment: 8
|Aug 13, 1999||FPAY||Fee payment|
Year of fee payment: 12
|Jan 18, 2000||AS||Assignment|
Owner name: LORAL CORPORATION, MARYLAND
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UNISYS CORPORATION;REEL/FRAME:010547/0468
Effective date: 19950505
|Feb 28, 2000||AS||Assignment|
Owner name: LOCKHEED MARTIN TACTICAL SYSTEMS, INC., MARYLAND
Free format text: CHANGE OF NAME;ASSIGNOR:LORAL CORP.;REEL/FRAME:010639/0395
Effective date: 19960423
|Mar 20, 2000||AS||Assignment|
Owner name: LOCKHEED MARTIN CORP., MARYLAND
Free format text: MERGER;ASSIGNOR:LOCKHEED MARTIN TACTICAL SYSTEMS, INC.;REEL/FRAME:010742/0857
Effective date: 19970627