|Publication number||USRE34444 E|
|Application number||US 07/725,353|
|Publication date||Nov 16, 1993|
|Filing date||Jul 3, 1991|
|Priority date||Jan 13, 1988|
|Publication number||07725353, 725353, US RE34444 E, US RE34444E, US-E-RE34444, USRE34444 E, USRE34444E|
|Inventors||Cecil H. Kaplinsky|
|Original Assignee||Xilinx, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Non-Patent Citations (8), Referenced by (102), Classifications (13), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Technical Field
The present invention relates to a class of integrated circuits known as programmable logic devices, whether mask programmable, fusible, ultraviolet erasable reprogrammable or electrically erasable reprogrammable, and in particular to architectures for programmable logic devices for optimizing speed and functional flexibility.
2. Background Art
Programmable logic devices (PLDs) are integrated circuits which increasingly are being used to provide the logic for electronic systems. For example, these devices may be used as "glue" to electrically connect and control the interaction of the major parts of a microcomputer system. Typically, PLDs include a set of input pins, two arrays of logic gates, i.e. an AND array followed by an OR array, and a set of output pins. Frequently, flip-flops following the OR array together with feedback lines are also included in order to provide registered output and sequential logic capabilities instead of the combinatorial logic provided by the AND/OR arrays alone.
Presently, several basic types of PLD architectures are available. In programmable logic elements (PLEs), the AND array is fixed and the OR array is programmable. PLEs are useful in applications requiring most or all possible input combinations, such as lookup tables and character generators. However, because the array size must be doubled for each additional input, PLEs are limited by cost and performance constraints to a small number of inputs. Programmable logic arrays (PLAs) have both a programmable AND array and a programmable OR array. Programmable array logic (PAL) devices have a programmable AND array, but a fixed OR array. Both the PLA and PAL architectures have advantages. Because both arrays are programmable, PLAs offer a high degree of functional flexibility. However, PAL are faster, because a programmable OR array is slower than dedicated OR gates. The PLA's flexibility is useful for complex state-machine and sequence applications, while most other applications not requiring a high degree of flexibility take advantage of the PAL's speed.
Some attempts have been made to combine both functional flexibility and speed in a PLD architecture. In Monolithic Memories' series of MEGAPALS, the size of the AND array was increased and a fixed number of AND product terms were allowed to be shared amongst two outputs. Altera's EP1200 chip is segmented into "sub-PALs" with only four outputs, the outputs of a particular segment being usable as inputs for only some of the sub-PALs. In each case, all of the inputs are available to all of the AND terms simultaneously, resulting in AND arrays with 64 inputs, most of which remaining unused for any given product term. Because of their fixed product terms, there are 16 product terms per OR gate. In practice, few sets of logic need so many inputs to an OR gate.
In U.S. Pat. No. 4,207,556, Sugiyama et al. discloses a programmable logic array arrangement having a plurality of cell units, each comprising a plurality of electronic elements, such as resistors, diodes and transistors, a wiring matrix of row and column lines, and an array unit having a group of switching elements for selectively interconnecting the various row and column lines, and electronic elements. The arrangement sacrifices density and speed for functionality by including a large number of electronic elements with variable wiring in each unit.
In Ikawa et al., "A One Day Chip: An Innovative IC Construction Approach . . . ", IEEE Journal of Solid-State Circuits, vol. Sc-21, No. 2, April 1986, pp. 223-227, a VLSI chip contains 50-200 standard logic functional blocks of SSI/MSI level integration performing various kinds of functions, such as inventors, NORs, NANDs, flip-flops, shift registers, counters, multipliers, ALUs, etc. Each of these fixed functional units may be connected to other functional units by means of an EEPROM switch matrix. The switch matrix provides flexibility and can easily be reprogrammed, but a large number of standard functional blocks must be anticipated to provide true flexibility, most of which would be unused for any given chip function.
An object of the present invention is to provide a programmable logic device architecture which makes good use of chip area, and combines functional flexibility with speed.
Another object of the present invention is to provide an architecture which can be exhaustively tested.
The above objects have been jet with a programmable logic device having a plurality of programmable functional units, each of which is similar to a PLA. Two fixed sets of conductive lines, one set permanently connected to the outputs of functional units, the other set permanently connected to the inputs of functional units, form programmable interconnection matrices where the two sets of conductive lines cross. Further, any of the input pins can be programmed to connect to any input of any functional unit, and any of the output pins can be programmed to connect to any output of any functional unit. A limited number of input pins can be connected to a functional unit, outputs of which are directly connected to a limited number of output pins, bypassing the interconnection matrices for speed.
Each interconnection matrix selectively connects the lines for each output of a functional unit to the lines for each input of the same or other functional unit. Typically, lines are connected by closing a switch, such as a fuse, EPROM or EEPROM. The input and output lines of interconnection matrices may be indirectly connected through an extra series switch for each input or output line. Thus, if there is a no connection only the capacitance of the series switch is seen, increasing the speed through an interconnection matrix.
Each functional unit may be configured like a conventional PLA with a number of inputs and outputs, AND and OR arrays, and possibly feedback lines, dedicated units and registers, edge triggered or enabled by a level. Alternatively, some or all of the functional units can be replaced by PALs, ROM, a discrete-logic ALU and the like. The OR array of a PLA can also be configured so that each AND product time is connectable via a switch to two different lines running through the OR array. One is a conventional product time line that may be selected for full functional flexibility, while the other is a line connected to only one, two or some other subset of OR lines that may be selected for speed. Alternatively, the OR may array may be only partially populated with programming links.
The architecture may include a pair of multiplexers connected respectively to the two sets of lines dedicated to functional unit inputs and outputs for separate access to individual functional units. This structure facilitates testing of the chip, since each functional unit can be exhaustively tested, then followed by testing of the interconnection matrix programming. A single large PLA can only be partially tested since the number of possible input combinations is too large for exhaustive testing. The lines from functional unit outputs can also be monitored by a programmable AND array and RAM for logic state analysis.
The programmable logic device may have an additional hierarchical level for even greater functionality, being made up of two or more subunits each having a matrix of functional units, conductive lines, input and output pins and interconnection matrices. The subunits are then connectable by a switching matrix in which control connect lines are programmably connected to conductive lines from functional unit outputs and to lines from the input pines and in which lead lines connected to the central connect lines are programmably connectable to conductive lines leading to functional unit inputs and to lines leading to output pins. Thus, any of the outputs from a functional unit in one subunit can be connected to any of the inputs to a functional unit in the other subunit. Input and output pins are likewise connected to functional units in the other subunit.
FIG. 1 is a schematic showing the basic structure of a programmable logic device of the present invention.
FIG. 2 is a schematic of a functional unit in the device of FIG. 1.
FIG. 3 is a schematic of an interconnection matrix in the device of FIG. 1.
FIG. 4 is a schematic of an output module in the device of FIG. 1.
FIG. 4a is a schematic of an alternative output module for the device of FIG. 1.
FIG. 5a is a closeup view of a portion of the interconnection matrix of FIG. 3. corresponding to a single output line.
FIG. 5b is a schematic of a portion corresponding to a single output line of an alternative interconnection matrix for use in the device of FIG. 1.
FIG. 6 is a closeup view of AND/OR arrays for a functional unit using a first alternative OR array arrangement.
FIG. 6a is a closeup view of a second alternative OR array arrangement.
FIG. 7 is a flow diagram illustrating the propagation times through the device of FIG. 1.
FIG. 8 is a schematic showing a second embodiment of a programmable logic device of the present invention having a direct path through the array.
FIG. 9 is a flow diagram illustrating the propagation times through the device of FIG. 8.
FIG. 10 is a schematic of a third embodiment of a programmable logic device in accord with the present invention.
FIG. 11 is a schematic of a fourth embodiment of a programmable logic device in accord with the present invention having a pair of multiplexers for functional unit level testing.
FIG. 12 is a schematic of a fifth embodiment of a programmable logic device of the present invention having elements for logic state analysis of the device.
FIG. 13 is a schematic of a sixth embodiment of a programmable logic device of the present invention.
FIG. 14 is a close-up view of an alternative functional unit for use in the device of FIG. 1.
With reference to FIG. 1, a programmable logic device includes a plurality of functional units 20-28. Preferably, the functional units 20-28 are arranged in a matrix of rows and columns. In the example given in FIG. 1, 9 functional units are shown, but the actual number may vary from device to device. Each functional unit includes a set of inputs 29 and a set of outputs 30. In the example in FIG. 1, each functional unit 20-28 has 12 inputs and 9 outputs. However, the number of inputs and outputs from the functional units may vary from device to device or within a device from functional unit to functional unit. Each functional unit performs one or more logic functions which when combined with logic functions from itself and other functional units produces the more complex function of the overall programmable logic device.
The programmable logic device also includes a first set of conductive lines, represented by the vertical lines 31 of multiplicity 9, which are permanently connected to the outputs 30 of functional units 20-28. Similarly, the device includes a second set of conductive lines, represented by the horizontal dashed lines 32 of multiplicity 12, which are permanently connected to the input lines 29 of functional units 20-28. Since each of the conductive lines either of the first set 31 or of the second set 32, is connected to the outputs or inputs of a particular functional unit, the multiplicity of these lines exactly matches the number of inputs or outputs of each functional unit. By the term "multiplicity" we mean that each of the lines and dashed lines represented in FIG. 1 is in actuality a collection of conductive lines whose number is indicated by the multiplicity. Thus the vertical solid line indicated by reference numeral 31 actually represents 9 conductive lines, each of which is connected to an output line 30 from functional unit 20. Likewise the horizontal dashed line indicated by reference numeral 32 is in actuality 12 conductive lines each permanently connected to an input 29 of functional unit 20. The actual multiplicity of each of the lines will depend on the number of inputs and outputs for each functional unit 20-28.
The two sets of conductive lines 31 and 32 cross at various areas of the programmable logic device to form programmable interconnection matrices 33. In the example given in FIG. 1, since one set of lines has a multiplicity of 9 and the other set of lines has a multiplicity of 12 the intersection of these two sets of lines forms matrices with 12×9 or 108 programmable crossings. Each of the crossings may be programmed to conduct or not conduct from one line to another by switches from one of a number of technologies. For example, each crossing into an interconnection matrix may be mask programmed at a Fab facility in accordance with a user's instructions by forming VIAs between two levels of crossing lines. Alternatively the interconnection matrices may be field programmable either by providing conductive fuses which may be broken by a user, or by providing EPROM or EEPROM switch transistors.
The programmable logic device also includes a set of input pints 34a and 34b. By "pins", we mean not only DIP-type pins but also other input and output constructions known in the art, such as the metallized contacts of flat chip carriers. In the example in FIG. 1, 16 input pins are provided. However, the number of input pins may vary from device to device. The sets of input pins 34a and 34b are permanently connected to conductive input lines 36a and 36b disposed to cross the second set of conductive lines 32. The crossings of input lines 36a and 36b with conductive lines 32 form programmable interconnection matrices 38. In FIG. 1, each of the interconnection matrices 38 is a 12 by 8 matrix of line crossings which may be made conductive by mask programming, fuse programming or switch programming with EPROMs or EEPROMs. In this manner each of the input pins 34a and 34b is selectively connected to any of the inputs 29 of functional units 20-28.
The programmable logic device also includes a set of output pins 40a and 40b. In FIG. 1, the number of output pints is 12. However, the number of output pins may vary from device to device. Output lines 42a and 42b are disposed to cross the first set of conductive lines 31 forming interconnection matrices 44 at the crossings. In the present example each interconnection matrix 44 is a 6 by 9 programmable array of switches, fuses or mask laid contacts. In this manner each of the output pins 40a and 40b may be connected to any output line 30 of any functional unit 20-28. Typically, the output lines 42a and 42b are not directly connected to output pins 40a and 40b, but are indirectly connected through output modules 46a and 46b. Input and output pins need not be distinct, as represented by line 47 connected a pair of pins 34a and 40a. Output modules 46a and 46b may be programmable logic arrays which can be used to generate data and control signals such as output enable and clock signals.
With reference to FIG. 2, each functional unit 20-28 in FIG. 1 may be a programmable logic array. As is known in the art a programmable logic array includes a programmable AND array 48 and a programmable OR array 50. These two arrays 48 and 50 combine to provide a two-step combinatorial logic. The PLA has a plurality of input lines 29a, 29b, . . . , 29l and a plurality of output lines 30a, 30b, . . . , 30i. In the present example, the number of input lines is 12 and the number of output lines is 9, but the actual number may vary from device to device and from functional unit to functional unit. The number of input and output lines is however considerably smaller than that of prior programmable logic devices using a single AND array and a single OR array for performing complex logic functions, since the programmable logic device architecture of the present invention breaks down the complex function into a number of simpler functions carried out by each programmable functional unit.
Each input line 29a-l passes through a pair of gates 52 and 54 which provide complementary signals. Each horizontal dashed line represents an AND gate, called a "product line". Each product line 56 is selectively connected to AND gate inputs 57 through programmable links 58. Links 58 may be mask programmed, fuse programmable or switch programmable. Each of the product lines 56 intersects OR input lines 60 leading to EXOR gate 62. Each intersection of a product line 56 and an OR input line 60 forms a programmable link 63 which again may be mask programmed, fuse programmable or switch programmable.
In the functional unit in FIG. 2 the output from EXOR gates 62 may be either directly connected to output lines 30a-i or connected through a flip-flop 64, the selection being made with a switch 63. Flip-flop 64 is a D-type flip-flop whose clock signal is determined by one of the product lines 56 connected via clock line 66. D-type flip-flops are commonly used in programmable logic devices to provide registered output. Other types of flip-flops and latches may also be used as well as feedback lines to either the AND array 48 or to input lines 29a-l. While functional units are preferably of the programmable logic array type, with both programmable AND and programmable OR arrays, they may also be of the other programmable logic device types with either fixed AND or fixed OR arrays.
FIG. 3 shows an interconnection matrix 33. Interconnection matrices 38 and 44 in FIG. 1 are of similar construction. Any of the first set of conductive lines 31, i.e., the conductive lines permanently connected to outputs 30 of functional units, shown in FIG. 3 as solid vertical lines 31a-i can be connected to any of the first set of conductive lines 32 i.e. those lines permanently connected to inputs 29 of functional units and shown as dashed horizontal lines 32a-l. Connection is made usually by closing a switch. In some cases, for example with fuses, the switch is closed until it is explicitly opened while with other switches such as EPROMs and EEPROMs the switch is open until it is explicitly closed. One hundred and eight switches 66 are shown in FIG. 3. The number of switches will vary from interconnection matrix to interconnection matrix, depending on the multiplicity of conductive lines 31 and 32.
With reference to FIGS. 4 and 4a, any selection of outputs from functional units can be connected to output pins 40 by means of an output module 46. Output module 46 includes an AND array 68 and an OR array 70 which can be programmed to control the outputs 40 by providing signals like output enable 76 and clock 74 as well as data signals 72 from output lines 42. Discrete logic output macrocells 78 generates the data output in response to clock and output enable signals 74 and 76. Other control signals might also be generated. Further, as seen in FIG. 4a, the data signals 72 need not go through the AND and OR array 68 and 70, but may instead connect directly to macrocells 78.
FIG. 5a shows one column 31a of interconnection matrix 33 in FIG. 3. Each switch 66 along conductive line 31a contributes capacitance to the overall circuit thereby slowing the circuit down. For example, conductive line 31a sees the capacitance of 12 switches 66 for connecting line 31a to the second set of conductive lines 32a-l. In the overall interconnection matrix shown in FIG. 3 there would be 108 switches present and a time delay of approximately 60 nanoseconds through the entire interconnection matrix. FIG. 5b shows a portion of a preferred interconnection matrix. Conductive line 31a is not directly connected to the second set of conductive lines 32a-l via switches 66, but is instead connected through extra series switches 81a' and 81a". In practice most conductive lines 31 from outputs will be connected to one or two conductive lines 32 to inputs. Only occasionally will there be more. In FIG. 5b series switch 81a' connects a main conductive line 31a to a branching conductive line 31a' while a second series switch 81a" connects main conductive line 31a to branching conductive line 31a". The branching lines 31a' and 31a" are then connected to second set of conductive lines 32a-l via switches 66. If no connection is made only the capacitance of the series witches 81a' and 8a" is seen. If one connection is made only the capacitance of one of the series switches 81a' or 81a" is seen together with only half of the remaining switches 66. Accordingly, if an output from a functional unit has a fanout of two, then it will see the inductance of only 30 switches instead of 108 switches. This approach can also be cascaded by defining the inputs into supergroups with a series switch to a supergroup and series switches to each group within the supergroup. The approach is not limited to outputs. The inputs could also be buffered from the inductance in the same way. That is, each conductive line of the second set may also comprise a main line and branching lines, with the branching lines being connected to the main line through series switches and connected to conductive lines of the first set, including possible branching lines of the first set, via additional switches or other programmable links.
OR arrays are useful because they allow two-stage logic to be used. PALs, with fixed ORs, also do this but at the expense of not being able to use product terms for multiple ORs. Product terms of PALs are committed to specific ORs and a product term not used in one AND/OR function cannot be used in another which may need extra ORs. A fixed OR is however faster and thus PALs trade off function for speed. Programmable OR terms in PLAs are slow for the same reason as the interconnection matrices, i.e. the capacitance of the switches. A programmable AND/OR array with an OR array 50' optimized for speed in shown in FIG. 6. Here the product terms 56 from AND array 48 can be connected via a switch 84 to two different lines 86 and 88 running through OR array 50'. Line 88 is a conventional product term which may be programmably connected via switches 90 to any of the input lines 92 to the OR gates of OR array 50. The second line, line 86, could be connected by a switch or switches 94 to some subset of OR terms. This arrangement allows the programmer to chose between the speed path 86 with some loss of product sharing or have a slower path 88 with full flexibility. This choice can be made for each product term 56.
In FIG. 6a, another OR array 50" is seen. Instead of using switches 84 as in FIG. 6 to choose the level of programmability, the product lines 56 connect to subsets only of OR gate input lines 60. In other words, the input lines 60 are only partially populated with programmable links 63 to product lines 56. For example, a typical arrangement for an AND/OR array, line that seen in FIG. 2 modified as in FIG. 6a to have OR input lines 60 only partially populated with links 63, includes 12 AND input lines, 44 product terms, 27 OR gate input lines (including input lines to latches or flip-flops 64) and 9 output lines. The OR gate input lines are grouped into threes, with two lines leading to an EXOR gate 62 and the third line serving as a clock for latch 64. The programmable links are typically staggered so that the first 12 product terms are connectable to the first group of three groups of three OR input lines, product terms 5-16 are connectable to the second group of OR input lines, product terms 9-20 are connectable to the third group of three groups of three OR input lines, and so forth, with the last 12 product terms 33-44 connectable to the ninth group of three groups of three OR input lines. Other partially populated arrangements of programmable links can also be constructed.
FIG. 7 shows the propagation time through a programmable logic device in accordance with the present invention, using the speed optimized programmable interconnection matrix described above with reference to FIG. 5b and functional units with optimized OR arrays as described above with reference to FIG. 6. From input pins 98 through input buffer 100 takes 4.5 nanoseconds. The propagation time through input switch matrix 102 takes 6 nanoseconds. The propagation time through the AND/OR array 104 of a functional unit takes 15 nanoseconds. The propagation time through flip-flop registers 106 takes 3 nanoseconds. The propagation time through output interconnection matrix 108 takes 6 nanoseconds and the time through output buffer 110 takes 7.5 nanoseconds. The total propagation time from input pins 98 to output pins 114 is 42 nanoseconds. The toggle propagation path 112 for propagation through additional functional units takes 24 nanoseconds per functional unit. This is a toggle rate of 40 MHz.
With reference to FIG. 8, a second embodiment of a programmable logic device in accordance with the present invention provides for a limited number of inputs a way of bypassing the interconnection matrices for a fast direct path to some output pins. In the example in FIG. 8, 10 out of 16 input pins, 8 input pins in a first group 34a and 2 input pins in a second group 34b, may be connected as before via input lines 36a and 36b and interconnection matrices 38 to inputs 29 of functional units 20-28. However 6 of the 16 input pins 34c may either be connected via input buffer 118, input lines 36c and interconnection matrices 39 to inputs 29 of functional units 20-28 or may be connected via multiplexer 117 to inputs 116 of a functional unit 122 performing a simple logic function. The outputs from functional unit 122 may be connected via buffer 120 to a set of conductive lines 121 to either additional functional units or output pins 40a and 40b through interconnection matrices. The outputs from function unit 122 may also be connected through conductive lines 124 to output pins 126 without going through any interconnection matrices. Output pins 126 are connected to conductive lines 124 or to the regular conductive lines 125 via a multiplexer 123.
As seen in FIG. 9, the bypass path 128 through AND/OR gate 122 has a total propagation time of 28 nanoseconds from input pins 98 through buffer 100 through functional unit 122 and then out through buffer 110 and output pins 114. This is considerably faster than the path taken through interconnection matrices 102 and 108 which, as mentioned above, is a duration of 42 nanoseconds. Such a fast path is useful, e.g., for enabling the appropriate memory devices in response to a high address bit from a CPU data request.
With reference to FIG. 10, functional units 22-28 for providing complex control logic need not be the only units present in the matrix of functional units. For example, a random access memory subunit 130 with a set of inputs for address, write, and enable, as well as a set of outputs for data, may be connected to the same sets of conductive lines 31 and 32 as other functional units. Similarly an arithmetic logic unit 132 with inputs A and B for operands and inputs F for operators as well as outputs for operation results may be connected in the same manner. Such an arrangement could integrate central processing units with their glue logic on the same chip.
Structures may be provided in a programmable logic device to facilitate testing of the programming. For example, with reference to FIG. 11, a pair of multiplexers 134 and 136 may be provided to access individual functional units 20-28. Multiplexer 134 is situated along an end of the first set of conductive lines 31 in order to access the outputs from functional units 20-28. A set of input pins 34a and pins A-G is temporarily dedicated to functional unit testing, and a set of output pins 40a is similarly temporarily dedicated. Pass gates 138 and 140 in response to signals along pins F and G enable input pins 34a and output pins 40a to interact with multiplexer 134. Signals along pins A, B, C and D determine which functional unit 20-28 is accessed. Multiplexer 136 is similarly connected to inputs to functional units 20-28 and is similarly controlled. Pass gates 139 and 141 in response to signals along pins J and H enable input pins 34b and output pins 40b to interact with multiplexer 136.
In operation, programming may be tested by first programming the functional units 20-28, leaving all interconnection matrices 33 open. Input lines 32 to functional units 20-28 are then driven by signals coming in from input pins 34b and multiplexer 136. Data, i.e. test results, are read out from output pins 40a via multiplexer 134 accessing output lines 31. Once the user is assured that each of the functional units 20-28 has been properly programmed and performs as expected, the interconnection matrices 33 are programmed. Interconnections are tested by accessing the same lines 31 and 32 via multiplexers 134 and 136. This procedure thus provides complete testability of all parts of the device, and works for all devices of the present invention using EPROM and EEPROM switches. This procedure does not work for devices having fuse links that are programmed by blowing, i.e. opening, connections, but does work for devices using links that are grown to close selected connections.
An advantage to accessing individual functional units 20-28 for testing is that since the functional units 20-28 have considerably fewer inputs they can be exhaustively tested. In the example in FIG. 11 each functional unit has 12 inputs so the total number of input combinations is 212 or 4,096 per functional unit. This means only 36,864 combinations need be tested for the entire device to be tested. A large programmable logic array could require up to 64 inputs to achieve the same level of function complexity as the present device. There would be no way to exhaustively test 264 possible input combinations in such a device.
Despite simulating the logic under a series of expected conditions, designers often encounter conditions that they have not taken into account. When they test the complete system or subsystem they find that it does not perform as expected. When SSI and MSI circuits are used, designers can "watch" the system perform, using instruments like oscilloscopes and logic state analyzers. However, they do not have access to the internal nodes of an integrated circuit so they cannot monitor what is actually happening in the same way as in the non-integrated case. Hence it is advantageous to add monitoring logic on a PLD, or a special variant of one produced for the testing phase, which will provide the monitoring information. An example of one such structure is shown in FIG. 12.
Referring then to FIG. 12, a programmable AND array 145 communicates with at least some, and typically all, of the output lines 31 from functional units 20-28, as well as lines 36a and 36b from input pins 34a and 34b. A random access memory (RAM) 147 communicates with AND array 145 and with two sets of pins 149 and 150. Address pins 149 are used from programming the AND array 145 and RAM 147 to record logic states when certain conditions are satisfied, while data pins 150 are used for reading out information recorded in RAM 147. In operation, when a programmed subset of output states on lines 31 and 36a-b meets a programmed condition, the AND array 145 detects this condition and transfers another programmed subset of output states to RAM 147, where these states are stored in selected memory addresses. When the programmed condition is not met, no information is recorded. The stored information can be read out from RAM 147 via data pins 150. Alternatively, data can be read out serially. The condition that triggers the recording of information can include an outside signal as shown by input pin 152 to the AND array 145. The trigger can be brought to the external world as shown by output pin 154 from the AND array to allow external conditions to be monitored as well.
With reference to FIG. 13, the programmable logic device architecture of the present invention can be extended to even higher densities by introducing an additional level of program hierarchy. A programmable logic device in FIG. 13 is composed of two halves or "subchips". More than two subchips could also be provided. A first subchip 160 comprises a plurality of functional units 20-28 with inputs 29 permanently connected to a set of conductive lines 32 and with outputs 30 permanently connected to a set of conductive lines 31. Conductive lines 31 and 32 cross at programmable interconnection matrices 33. Sets of input pins 34a and 34b connect to conductive lines 32 via input lines 36a and 36b and interconnection matrices 38, and sets of output pins 40a and 40b connect to conductive lines 31 via output modules 46a and 46b, output lines 42a and 42b and interconnection matrices 44. A second subchip 162 likewise constructed with functional units 20a-28a having inputs and outputs 29 and 30, conductive lines 31 and 32, input pins 34c and 34d, input lines 36c and 36d, output pins 40c and 40d, output modules 46c and 46d, output lines 42c and 42d, and associated interconnection matrices.
A programmable switching matrix 163 connects the two subchips 160 and 162, so that any signal in one subchip can be connected anywhere else, though not all simultaneously. Switching matrix 164 includes a set of central connect lines, represented by horizontal dashed lines 166, each of plural multiplicity, and two sets of lead lines, represented by vertical lines 168 and 169, again of plural multiplicity. Input lines 36a-d and conductive lines 31 from functional unit outputs 30 cross the central connect lines 166 at programmable interconnection matrices 170. Likewise, lead lines 168 and 169 cross central connect lines 166 at interconnection matrices 172, which may be either fixed or programmable. Lead lines 168 and 169 also cross conductive lines 32 leading to functional unit inputs 29 of respective first and second subchips 160 and 162, at programmable interconnection matrices 174.
Accordingly, input pins 34a and 34b may be programmed to connect to functional unit inputs 29 of first subchip 160 directly through input lines 36a and 36b and conductive lines 32 or to functional unit inputs of second subchip 162 through input lines 36a and 36b, central connect lines 166 and lead lines 169 of switch matrix 164, then through conductive lines 32 on the second subchip 162. Likewise, input pins 36c and 36d can be programmed to connect to functional unit inputs of second subchip 162 directly or to functional unit inputs of first subchip 160 indirectly through central connect lines 166 and lead lines 168 of switch matrix 164. Conductive lines 31 from functional unit outputs 30 on one subchip can also be programmed via switch matrix 164 to connect with conductive lines 32 leading to functional unit inputs 29 or to output lines 42a-d leading to output pins 40a-d on the other subchip.
With reference to FIG. 14, there are some frequently used arithmetic and logic functions which cannot easily or quickly be done with a small number of product terms using an AND/OR array. Addition and testing a result for zero are two examples. Consider, for example, the addition of two numbers A and B to obtain a sum S. The nth bit of the sum Sn is Sn =(An ·˜Bn ·OR·˜An ·Bn-)·EXOR·Cn-1, where Cn-1 =An-1 ·Bn-1 ·OR·An-1 ·Cn-2 ·OR·Bn-1 ·Cn-2 is the carry in from a previous computation stage. The carry term can be calculated sequentially, i.e., by a "ripple carry", by feeding the previous carry term back into the array. Unfortunately, this means that multiple passes through the array need to be done, which may not be fast enough in many situations. An alternative is to generate all of the carry terms simultaneously. ##EQU1## It is easily seen that the number of terms increases geometrically and that 52 product terms will be needed just to calculate the first four carry terms.
The functional unit in FIG. 14 uses some additional specialized logic at the output of the sum terms to help in this calculation. This functional unit comprises an AND array 178, generating product terms 179, and an OR array 180 having OR gate input lines 183 programmable connected to the product terms 179 and leading into OR gates 184, in the present case exclusive OR gates. The functional unit also contains latches or flip-flops 186 which can be programmed by a switch 187 to either always pass the outputs from the OR gates to the functional unit outputs 188 or to act as a register in response to clock lines 185. The OR array 180 can be partially populated with programmable links 189, as shown, can be fully populated as in FIG. 1, or can have branched product terms as in FIG. 6.
In addition to this AND/OR array, the functional unit also has a specialized unit 182 with dedicated logic. In the unit shown in FIG. 14, the specialized unit 182 aids in performing addition. However in other instances the specialized unit may have dedicated logic for performing some other functions. In the presence instance, the specialized unit determines the carry term Cn =An ·Bn ·OR·An ·Cn-1 ·OR·Bn ·Cn-1, and thereby allows addition to be done with just four product terms, An ·˜Bn, ˜An ·Bn, An-1 and Bn-1. Specialized unit 182 is only used where needed and is programmably linked to the remainder of the AND/OR array by an EPROM switch 190.
The programmable logic device architecture of the present invention achieves a large amount of functional flexibility combined with high speed and low cost by providing individually programmable functional units. with a fixed set of wiring forming interconnection matrices which also can be individually programmed. Further, by providing a fast path through the chip many logic functions can be performed without considerable delay. Additional hierarchical levels for the device, as well as dedicated units programmably connectable to Functional unit AND/OR arrays, provide increased functionality. Individual access to functional units and logic state recording facilitates exhaustive testing of the device.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4124899 *||May 23, 1977||Nov 7, 1978||Monolithic Memories, Inc.||Programmable array logic circuit|
|US4207556 *||Dec 5, 1977||Jun 10, 1980||Nippon Telegraph And Telephone Public Corporation||Programmable logic array arrangement|
|US4314349 *||Dec 31, 1979||Feb 2, 1982||Goodyear Aerospace Corporation||Processing element for parallel array processors|
|US4414547 *||Oct 16, 1981||Nov 8, 1983||General Instrument Corporation||Storage logic array having two conductor data column|
|US4422072 *||Jul 30, 1981||Dec 20, 1983||Signetics Corporation||Field programmable logic array circuit|
|US4431928 *||Jun 22, 1981||Feb 14, 1984||Hewlett-Packard Company||Symmetrical programmable logic array|
|US4609986 *||Jun 14, 1984||Sep 2, 1986||Altera Corporation||Programmable logic array device using EPROM technology|
|US4642487 *||Sep 26, 1984||Feb 10, 1987||Xilinx, Inc.||Special interconnect for configurable logic array|
|US4670749 *||Apr 13, 1984||Jun 2, 1987||Zilog, Inc.||Integrated circuit programmable cross-point connection technique|
|US4763020 *||Sep 4, 1986||Aug 9, 1988||Ricoh Company, Ltd.||Programmable logic device having plural programmable function cells|
|1||"Technology to Watch: Programmable Logic Devices", Electronics, Sep. 17, 1987, pp. 65-72.|
|2||Ikawa et al., "A One-Day Chip: An Innovative IC Construction Approach . . . ", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 2, Apr. 1986, pp. 223-227.|
|3||*||Ikawa et al., A One Day Chip: An Innovative IC Construction Approach . . . , IEEE Journal of Solid State Circuits, vol. SC 21, No. 2, Apr. 1986, pp. 223 227.|
|4||P. Robinson, "Overview of Programmable Hardwar", Byte, Jun. 1987, pp. 197-203.|
|5||*||P. Robinson, Overview of Programmable Hardwar , Byte, Jun. 1987, pp. 197 203.|
|6||*||Technology to Watch: Programmable Logic Devices , Electronics, Sep. 17, 1987, pp. 65 72.|
|7||V. Coli, "Introduction to Programmable Array Logic", Byte, Jan. 1987, pp. 207-219.|
|8||*||V. Coli, Introduction to Programmable Array Logic , Byte, Jan. 1987, pp. 207 219.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5519629 *||May 1, 1995||May 21, 1996||Hewlett-Packard Company||Tileable gate array cell for programmable logic devices and gate array having tiled gate array cells|
|US5570040 *||Mar 22, 1995||Oct 29, 1996||Altera Corporation||Programmable logic array integrated circuit incorporating a first-in first-out memory|
|US5572148 *||Mar 22, 1995||Nov 5, 1996||Altera Corporation||Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory|
|US5684413 *||Mar 28, 1996||Nov 4, 1997||Philips Electronics North America Corp.||Condensed single block PLA plus PAL architecture|
|US5684980 *||Jul 23, 1996||Nov 4, 1997||Virtual Computer Corporation||FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions|
|US5757207 *||May 6, 1996||May 26, 1998||Altera Corporation||Programmable logic array integrated circuit incorporating a first-in first-out memory|
|US5857109 *||Apr 11, 1995||Jan 5, 1999||Giga Operations Corporation||Programmable logic device for real time video processing|
|US6018490 *||Oct 9, 1998||Jan 25, 2000||Altera Corporation||Programmable logic array integrated circuits|
|US6023439 *||Sep 17, 1998||Feb 8, 2000||Altera Corporation||Programmable logic array integrated circuits|
|US6064599 *||Oct 26, 1998||May 16, 2000||Altera Corporation||Programmable logic array integrated circuits|
|US6128692 *||Jun 11, 1998||Oct 3, 2000||Altera Corporation||Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices|
|US6134173 *||Nov 2, 1998||Oct 17, 2000||Altera Corporation||Programmable logic array integrated circuits|
|US6218860||May 17, 1999||Apr 17, 2001||Altera Corporation||Programmable logic array integrated circuit incorporating a first-in first-out memory|
|US6219284||Sep 24, 1999||Apr 17, 2001||Altera Corporation||Programmable logic device with multi-port memory|
|US6242946||Aug 5, 1999||Jun 5, 2001||Altera Corporation||Embedded memory block with FIFO mode for programmable logic device|
|US6259588||Dec 29, 1999||Jul 10, 2001||Altera Corporation||Input/output buffer with overcurrent protection circuit|
|US6262933||Jan 28, 2000||Jul 17, 2001||Altera Corporation||High speed programmable address decoder|
|US6285211||Dec 13, 1999||Sep 4, 2001||Altera Corporation||I/O buffer circuit with pin multiplexing|
|US6289494||Nov 12, 1997||Sep 11, 2001||Quickturn Design Systems, Inc.||Optimized emulation and prototyping architecture|
|US6340897||Jan 11, 2000||Jan 22, 2002||Altera Corporation||Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory|
|US6369608||Jan 18, 2001||Apr 9, 2002||Xillinx, Inc.||Conditioning semiconductor-on-insulator transistors for programmable logic devices|
|US6459303||Apr 9, 2001||Oct 1, 2002||Altera Corporation||High speed programmable address decoder|
|US6467017||Jul 29, 1998||Oct 15, 2002||Altera Corporation||Programmable logic device having embedded dual-port random access memory configurable as single-port memory|
|US6486702||Jun 30, 2000||Nov 26, 2002||Altera Corporation||Embedded memory blocks for programmable logic|
|US6570404||Mar 26, 1997||May 27, 2003||Altera Corporation||High-performance programmable logic architecture|
|US6593772||Jun 19, 2002||Jul 15, 2003||Altera Corporation||Embedded memory blocks for programmable logic|
|US6625793||Sep 6, 2001||Sep 23, 2003||Quickturn Design Systems, Inc.||Optimized emulation and prototyping architecture|
|US6720796||May 6, 2002||Apr 13, 2004||Altera Corporation||Multiple size memories in a programmable logic device|
|US6759870||Feb 20, 2003||Jul 6, 2004||Altera Corporation||Programmable logic array integrated circuits|
|US6882176||Mar 7, 2003||Apr 19, 2005||Altera Corporation||High-performance programmable logic architecture|
|US6897679||Jan 31, 2003||May 24, 2005||Altera Corporation||Programmable logic array integrated circuits|
|US7058534 *||Mar 19, 2003||Jun 6, 2006||Altera Corporation||Method and apparatus for application specific test of PLDs|
|US7111110||Dec 10, 2002||Sep 19, 2006||Altera Corporation||Versatile RAM for programmable logic device|
|US7245606 *||Dec 6, 2002||Jul 17, 2007||Nxp Bv||Switching device comprising a common voltage reference path|
|US7340596||Jun 12, 2001||Mar 4, 2008||Altera Corporation||Embedded processor with watchdog timer for programmable logic|
|US7350178||Aug 27, 2004||Mar 25, 2008||Altera Corporation||Embedded processor with watchdog timer for programmable logic|
|US7394284 *||Sep 8, 2003||Jul 1, 2008||Pact Xpp Technologies Ag||Reconfigurable sequencer structure|
|US7434191||Sep 18, 2002||Oct 7, 2008||Pact Xpp Technologies Ag||Router|
|US7480763||Aug 28, 2006||Jan 20, 2009||Altera Corporation||Versatile RAM for a programmable logic device|
|US7565525||Mar 1, 2004||Jul 21, 2009||Pact Xpp Technologies Ag||Runtime configurable arithmetic and logic cell|
|US7577822||Sep 9, 2002||Aug 18, 2009||Pact Xpp Technologies Ag||Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization|
|US7584390||Jan 14, 2004||Sep 1, 2009||Pact Xpp Technologies Ag||Method and system for alternating between programs for execution by cells of an integrated circuit|
|US7595659||Oct 8, 2001||Sep 29, 2009||Pact Xpp Technologies Ag||Logic cell array and bus system|
|US7602214||Apr 7, 2008||Oct 13, 2009||Pact Xpp Technologies Ag||Reconfigurable sequencer structure|
|US7650448||Jan 10, 2008||Jan 19, 2010||Pact Xpp Technologies Ag||I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures|
|US7657861||Jul 23, 2003||Feb 2, 2010||Pact Xpp Technologies Ag||Method and device for processing data|
|US7657877||Jun 20, 2002||Feb 2, 2010||Pact Xpp Technologies Ag||Method for processing data|
|US7782087||Aug 14, 2009||Aug 24, 2010||Martin Vorbach||Reconfigurable sequencer structure|
|US7822881||Oct 7, 2005||Oct 26, 2010||Martin Vorbach||Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)|
|US7822968||Feb 10, 2009||Oct 26, 2010||Martin Vorbach||Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs|
|US7840842||Aug 3, 2007||Nov 23, 2010||Martin Vorbach||Method for debugging reconfigurable architectures|
|US7844796||Aug 30, 2004||Nov 30, 2010||Martin Vorbach||Data processing device and method|
|US7899962||Dec 3, 2009||Mar 1, 2011||Martin Vorbach||I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures|
|US7928763||Jul 14, 2010||Apr 19, 2011||Martin Vorbach||Multi-core processing system|
|US7996827||Aug 16, 2002||Aug 9, 2011||Martin Vorbach||Method for the translation of programs for reconfigurable architectures|
|US8058899||Feb 13, 2009||Nov 15, 2011||Martin Vorbach||Logic cell array and bus system|
|US8069373||Jan 15, 2009||Nov 29, 2011||Martin Vorbach||Method for debugging reconfigurable architectures|
|US8099618||Oct 23, 2008||Jan 17, 2012||Martin Vorbach||Methods and devices for treating and processing data|
|US8127061||Feb 18, 2003||Feb 28, 2012||Martin Vorbach||Bus systems and reconfiguration methods|
|US8145881||Oct 24, 2008||Mar 27, 2012||Martin Vorbach||Data processing device and method|
|US8156284||Jul 24, 2003||Apr 10, 2012||Martin Vorbach||Data processing method and device|
|US8156312||Jun 19, 2007||Apr 10, 2012||Martin Vorbach||Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units|
|US8195856||Jul 21, 2010||Jun 5, 2012||Martin Vorbach||I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures|
|US8209653||Oct 7, 2008||Jun 26, 2012||Martin Vorbach||Router|
|US8230411||Jun 13, 2000||Jul 24, 2012||Martin Vorbach||Method for interleaving a program over a plurality of cells|
|US8250503||Jan 17, 2007||Aug 21, 2012||Martin Vorbach||Hardware definition method including determining whether to implement a function as hardware or software|
|US8281108||Jan 20, 2003||Oct 2, 2012||Martin Vorbach||Reconfigurable general purpose processor having time restricted configurations|
|US8281265||Nov 19, 2009||Oct 2, 2012||Martin Vorbach||Method and device for processing data|
|US8301872||May 4, 2005||Oct 30, 2012||Martin Vorbach||Pipeline configuration protocol and configuration unit communication|
|US8312200||Jul 21, 2010||Nov 13, 2012||Martin Vorbach||Processor chip including a plurality of cache elements connected to a plurality of processor cores|
|US8312301||Sep 30, 2009||Nov 13, 2012||Martin Vorbach||Methods and devices for treating and processing data|
|US8407525||Oct 24, 2011||Mar 26, 2013||Pact Xpp Technologies Ag||Method for debugging reconfigurable architectures|
|US8429385||Sep 19, 2002||Apr 23, 2013||Martin Vorbach||Device including a field having function cells and information providing cells controlled by the function cells|
|US8468329||Jun 8, 2012||Jun 18, 2013||Martin Vorbach||Pipeline configuration protocol and configuration unit communication|
|US8471593||Nov 4, 2011||Jun 25, 2013||Martin Vorbach||Logic cell array and bus system|
|US8686475||Feb 9, 2011||Apr 1, 2014||Pact Xpp Technologies Ag||Reconfigurable elements|
|US8686549||Sep 30, 2009||Apr 1, 2014||Martin Vorbach||Reconfigurable elements|
|US8726250||Mar 10, 2010||May 13, 2014||Pact Xpp Technologies Ag||Configurable logic integrated circuit having a multidimensional structure of configurable elements|
|US8803552||Sep 25, 2012||Aug 12, 2014||Pact Xpp Technologies Ag||Reconfigurable sequencer structure|
|US8812820||Feb 19, 2009||Aug 19, 2014||Pact Xpp Technologies Ag||Data processing device and method|
|US8819505||Jun 30, 2009||Aug 26, 2014||Pact Xpp Technologies Ag||Data processor having disabled cores|
|US8869121||Jul 7, 2011||Oct 21, 2014||Pact Xpp Technologies Ag||Method for the translation of programs for reconfigurable architectures|
|US8914590||Sep 30, 2009||Dec 16, 2014||Pact Xpp Technologies Ag||Data processing method and device|
|US9037807||Nov 11, 2010||May 19, 2015||Pact Xpp Technologies Ag||Processor arrangement on a chip including data processing, memory, and interface elements|
|US9047440||May 28, 2013||Jun 2, 2015||Pact Xpp Technologies Ag||Logical cell array and bus system|
|US9075605||Oct 17, 2012||Jul 7, 2015||Pact Xpp Technologies Ag||Methods and devices for treating and processing data|
|US9092595||Nov 17, 2014||Jul 28, 2015||Pact Xpp Technologies Ag||Multiprocessor having associated RAM units|
|US9141390||Sep 29, 2014||Sep 22, 2015||Pact Xpp Technologies Ag||Method of processing data with an array of data processors according to application ID|
|US9170812||Dec 16, 2014||Oct 27, 2015||Pact Xpp Technologies Ag||Data processing system having integrated pipelined array data processor|
|US9250908||Jun 27, 2014||Feb 2, 2016||Pact Xpp Technologies Ag||Multi-processor bus and cache interconnection system|
|US9274984||Aug 12, 2014||Mar 1, 2016||Pact Xpp Technologies Ag||Multi-processor with selectively interconnected memory units|
|US9436631||Mar 31, 2014||Sep 6, 2016||Pact Xpp Technologies Ag||Chip including memory element storing higher level memory data on a page by page basis|
|US9552047||Mar 19, 2014||Jan 24, 2017||Pact Xpp Technologies Ag||Multiprocessor having runtime adjustable clock and clock dependent power supply|
|US9690747||May 13, 2014||Jun 27, 2017||PACT XPP Technologies, AG||Configurable logic integrated circuit having a multidimensional structure of configurable elements|
|US20020130681 *||Aug 22, 2001||Sep 19, 2002||Cliff Richard G.||Programmable logic array integrated circuits|
|US20030118032 *||Dec 6, 2002||Jun 26, 2003||Philippe Barre||Switching device comprising a common voltage reference path|
|US20040066212 *||Jan 31, 2003||Apr 8, 2004||Altera Corporation||Programmable logic array integrated circuits|
|US20100272811 *||Jul 23, 2009||Oct 28, 2010||Alkermes,Inc.||Complex of trospium and pharmaceutical compositions thereof|
|USRE40011||Oct 19, 2001||Jan 22, 2008||Altera Corporation||System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly|
|USRE44365||Oct 21, 2010||Jul 9, 2013||Martin Vorbach||Method of self-synchronization of configurable elements of a programmable module|
|USRE45109||Oct 21, 2010||Sep 2, 2014||Pact Xpp Technologies Ag||Method of self-synchronization of configurable elements of a programmable module|
|USRE45223||Oct 21, 2010||Oct 28, 2014||Pact Xpp Technologies Ag||Method of self-synchronization of configurable elements of a programmable module|
|International Classification||H04Q3/52, H03K19/177|
|Cooperative Classification||H03K19/17736, H03K19/17792, H04Q3/521, H03K19/17728, H03K19/17704|
|European Classification||H03K19/177F, H03K19/177J6, H03K19/177D2, H03K19/177B, H04Q3/52K|
|Dec 16, 1996||FPAY||Fee payment|
Year of fee payment: 8
|Oct 23, 2000||FPAY||Fee payment|
Year of fee payment: 12