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Publication numberUSRE34463 E
Publication typeGrant
Application numberUS 07/662,663
Publication dateNov 30, 1993
Filing dateFeb 28, 1991
Priority dateDec 6, 1985
Fee statusPaid
Publication number07662663, 662663, US RE34463 E, US RE34463E, US-E-RE34463, USRE34463 E, USRE34463E
InventorsYasuhiro Konishi, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Hideto Hidaka, Katsumi Dosaka
Original AssigneeMitsubishi Denki Kabushiki Kaisha
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor memory device with active pull up
US RE34463 E
Abstract
A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential VCC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to VCC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.
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Claims(10)
What is claimed is:
1. A semiconductor memory device comprising:
a plurality of pairs of bit lines;
a plurality of word lines provided to intersect with said plurality of pairs of bit lines;
a plurality of memory cells each provided in correspondence to the intersection point between each said pair of bit lines and each said word line to be connected with said pair of bit lines and said word line;
precharge means provided for each said pair of bit lines to precharge potentials of said pair of bit .[.lies173 .Iadd.lines .Iaddend.at a first constant potential;
memory cell selection/readout means for selecting a memory cell for reading data by selecting said word line after precharging of said pair of bit lines by said precharge means and reading data from said selected memory cell on said pair of bit lines;
sense amplifier means provided for each said pair of bit lines for detecting potentials of said pair of bit lines upon reading of said data from said selected memory cell to lower the potential of a lower level one of said pair of bit lines to a second constant potential;
means for supplying an external row address strobe signal having a constant duration;
delay means for delaying said external row address strobe signal by a prescribed period;
internal row address strobe signal generating means for generating an internal row address strobe signal having a trailing edge obtained by delaying the trailing edge of said external row address strobe signal by said prescribed period in response to said external row address strobe signal and the output from said delay means, said internal row address strobe signal alternately repeatedly .Iadd.defining a non-active cycle for the operation of said .Iaddend.precharge means and an active cycle for the operations of said memory cell selection/readout means and said sense amplifier means; and
active pull-up means provided for each said pair of bit lines for pulling up said potential of said higher level one of said pair of bit lines from starting of the operation of said sense amplifier means to termination of said active cycle defined by said internal row address strobe signal to a third contact potential.
2. A semiconductor memory device in accordance with claim 1, wherein
said first and third constant potentials are at a supply potential level and said second constant potential is at a ground potential level.
3. A semiconductor memory device in accordance with claim 1, wherein
said second constant potential is at a ground potential level and said third constant potential is at a supply potential level, while said first constant potential is at an intermediate potential level between said second constant potential and said third constant potential.
4. A semiconductor memory device in accordance with claim 1, wherein
said delay means is formed by a plurality of inverters connected in the series form.
5. A semiconductor memory device in accordance with claim 1, wherein
said internal row address strobe signal generating means is a NAND circuit for receiving said external row address strobe signal and the output from said delay means. .Iadd.
6. A semiconductor memory device comprising:
a plurality of pairs of bit lines;
a plurality of word lines provided to intersect with said plurality of pairs of bit lines;
a plurality of memory cells each provided in correspondence to the intersection point between each said pair of bit lines and each said word line to be connected with said pair of bit lines and said word line;
precharge means provided for each said pair of bit lines to precharge potentials of said pair of bit lines at a first constant potential;
a memory cell selection/readout means for selecting a memory cell for reading data by selecting said word line after precharging of said pair of bit lines by said precharge means and reading data from said selected memory cell on said pair of bit lines;
sense amplifier means provided for each said pair of bit lines for detecting potentials of said pair of bit lines upon reading of said data from said selected memory cell to lower the potential of a lower level one of said pair of bit lines to a second constant potential;
means for supplying an external row address strobe signal having a constant duration;
delay means for delaying said external row address strobe signal by a prescribed period;
internal control signal generating means for generating an internal control signal having a trailing edge obtained by delaying the trailing edge of said external row address strobe signal by said prescribed period in response to said external row address strobe signal and the output from said delay means, said internal control signal alternately repeatedly controlling a non-active cycle for the operation of said precharge means and an active cycle for the operations of said memory cell selection/readout means and said sense amplifier means; and
active pull-up means provided for each said pair of bit lines for pulling up said potential of said higher level one of said pair of bit lines after starting of the operation of said sense amplifier means to termination of said active cycle defined by said internal control signal to a third constant potential. .Iaddend. .Iadd.
7. A semiconductor memory device in accordance with claim 6, wherein
said second constant potential is at a ground potential level and said third constant potential is at a supply potential level, while said first constant potential is at an intermediate potential level between said second constant potential and said third constant potential. .Iaddend. .Iadd.8. A semiconductor memory device in accordance with claim 6, wherein
said delay means comprises a plurality of inverters connected in series. .Iaddend. .Iadd.9. A semiconductor memory device in accordance with claim 6, wherein
said internal control signal generating means comprises a NAND circuit for receiving said external row address strobe signal and the output from said delay means. .Iaddend. .Iadd.10. A semiconductor memory device in accordance with claim 6, wherein said internal control signal controls at least said precharge means, said sense amplifier means and said active
pull-up means. .Iaddend. .Iadd.11. A semiconductor memory device comprising:
a plurality of memory cells arranged in a matrix having rows and columns;
a plurality of word lines arranged in rows, wherein each word line is connected to respective ones of said memory cells arranged in a corresponding row of said matrix;
a plurality of pairs of bit lines arranged in columns, wherein one bit line of each pair of bit lines is connected to respective ones of said memory cells arranged in a corresponding column of said matrix;
a plurality of sense amplifier means arranged in columns, wherein each sense amplifier means is connected to a pair of said bit lines arranged in a corresponding column, for detecting a difference between potentials appearing on said pair of bit lines arranged in the corresponding column and pulling down a potential of a lower level bit line of said pair of bit lines to a lower constant potential;
a plurality of active pull-up means arranged in columns, wherein each active pull-up means is connected to said pair of bit lines arranged in the corresponding column, for pulling up the potential of the higher level bit line of said pair of bit lines, which is detected by said sense amplifier means as the difference between potentials to a higher constant potential;
means for receiving an external row address strobe signal having a first edge changing from a first level to a second level and a second edge changing from said second level to said first level; and
means for generating an active pull-up activating signal having a first edge changing from a third level to a fourth level and a second edge changing from said fourth level to said third level, wherein said active pull-up activating signal is connected for activating said active pull-up means in a time between the first edge thereof and the second edge thereof, the first edge of said active pull-up activating signal occurring after detecting by said sense amplifier of a difference between potentials appearing on said pair of bit lines, the second edge of said active pull-up activating signal occurring at a time after passing of a predetermined period from occurrence of said second edge of said external
row address strobe signal. .Iaddend. .Iadd.12. A semiconductor memory device in accordance with claim 11, wherein said lower constant potential is at a ground potential level and said higher constant potential is at a
supply potential level. .Iaddend. .Iadd.13. A semiconductor memory device in accordance with claim 11, including means of obtaining the second edge of said active pull-up activating signal by delaying the second edge of said external row address strobe signal by said predetermined period in response to the second edge of said external row address strobe signal. .Iaddend. .Iadd.14. A semiconductor memory device in accordance with claim 11, further comprising means for generating a sense amplifier activating signal having a first edge changing from a fifth level to a sixth level and a second edge changing from said sixth level to said fifth level, wherein said sense amplifier activating signal is connected for activating said sense amplifier means in a time between the first edge thereof and the second edge thereof, the first edge of said sense amplifier activating signal occurring at a time between occurrence of the first edge of said external row strobe signal and occurrence of the first edge of said active pull-up activating signal, the second edge of said means sense amplifier activating signal occurring at substantially the same time as the occurrence of said second edge of said active pull-up activating signal. .Iaddend.
Description

.Iadd.This is a Reissue of Ser. No. 06/938,065, filed Dec. 4, 1986 now U.S. Pat. No. 4,809,230.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and more particularly, it relates to improvement in a semiconductor memory device such as a MOS (metal oxide semiconductor) dynamic type RAM (random access memory) provided with active pull-up circuits.

2. Description of the Prior Art

In general, a MOS dynamic type RAM comprises a plurality of pairs of bit lines and a sense amplifier provided for each pair of bit lines. Before reading out information from a memory cell, the potentials of a corresponding pair of bit lines are precharged to a supply potential VCC . When the memory cell for reading information is selected to cause small potential difference between the corresponding pair of bit lines, the potential of the lower level one of the bit line pair is lowered to a ground potential VSS by the sense amplifier. Thus, the sense amplifier is adapted to detect and amplify the small potential difference between the corresponding pair of bit lines thereby to read information from the memory cell. In practice, however, the higher level one of the bit line pair may be slightly lowered by discharge upon starting of the aforementioned sensing operation or current leakage after completion of the sensing operation. In such case, the level of rewriting in the memory cell is also lowered, and hence the conventional MOS dynamic type RAM may be provided with active pull-up circuits. Each active pull-up circuit is adapted to raise only the potential of the higher level bit line to the supply potential VCC. For example, U.S. Pat. No. 4,291,392 discloses a dynamic type memory device provided with such active pull-up circuits.

On the other hand the precharge level may be set at the intermediate level between the supply potential VCC and the ground potential VSS in order to reduce supply current when the bit line is charged or discharged, and also in this case, the potential of the higher level bit line must be raised to the supply potential level VCC by an active pull-up circuit.

FIG. 1 is a circuit diagram schematically showing an example of a conventional MOS dynamic type RAM provided with active pull-up circuit.

Description is now made on the structure of the circuit as shown in FIG. 1.

Referring to FIG. 1, a pair of bit lines BL and BL are provided to intersect with a word line WL and a dummy word line DWL respectively. A memory cell 10 is connected to the word line WL and the bit line BL, while a dummy cell 11 is connected to the dummy word line DWL and the bit line BL. In further detail, the memory cell 10 is formed by a MOS transistor 4 and a capacitor 8 of capacitance CM, and the MOS transistor 4 has a first electrode connected with the bit line BL, a second electrode connected with a cell plate electrode CP through the capacitor 8 and a gate electrode connected with the word line WL. The dummy cell 11 is formed by a MOS transistor 5 and a capacitor 9 of capacitance CD, and the MOS transistor 5 has a first electrode connected with the bit line BL, a second electrode connected with a cell plate electrode CP through the capacitor 9 and a gate electrode connected with the dummy word line DWL.

Further, a series circuit of MOS transistors 6 and 7 is connected between the pair of bit lines BL and BL. The MOS transistor 6 has a first electrode connected with the bit line BL and a second electrode connected with a first electrode of the MOS transistor 7. A second electrode of the MOS transistor 7 is connected with the bit line BL. A precharge potential VP (=1/2VCC) is applied to the juncture between the second electrode of the MOS transistor 6 and the first electrode of the MOS transistor 7 for precharging the potentials of the pair of bit lines BL and BL. The MOS transistors 6 and 7 are on-off controlled by a precharge signal Φp applied to the respective gate electrodes thereof.

On the other hand, a sense amplifier 12 formed by MOS transistors 1 and 2 is connected between the pair of bit lines BL and BL. A first electrode of the MOS transistor 1 is connected with the bit line BL and a second electrode thereof is connected with a first electrode of the MOS transistor 2. A second electrode of the MOS transistor 2 is connected with the bit line BL. The gate electrode of the MOS transistor 1 is connected with the bit line BL, and the gate electrode of the MOS transistor 2 is connected with the bit line BL. The juncture between the second electrode of the MOS transistor 1 and the first electrode of the MOS transistor 2 is grounded through a MOS transistor 3. The MOS transistor 3 is on-off controlled by a sense amplifier activating signal S0 applied to its gate electrode. Namely, the operation of the sense amplifier 12 is controlled by the sense amplifier activating signal S0 to detect the potentials of the pair of bit lines BL and BL and lower the potential of the lower level bit line to a ground potential VSS.

Further, an active pull-up circuit 13 is connected between the pair of bit lines BL and BL. This active pull-up circuit 13 is controlled by an active pull-up signal AR, to pull up the potential of the higher level one of the pair of bit lines BL and BL to the supply potential VCC.

For the sake of convenience, FIG. 1 shows only one pair of bit lines, one word line, one dummy word line, one memory cell, one dummy cell, a group of precharging MOS transistors and one active pull-up circuit. However, an actual MOS dynamic type RAM is provided with a plurality of pairs of bit lines intersecting with a plurality of word lines and a plurality of dummy word lines. A memory cell is connected between one of each pair of bit lines and each word line. Further, a dummy cell is connected to each dummy word line for each pair of bit lines. Such memory cells and dummy cells are arrayed in the form of a matrix to form a memory cell array. Further, a group of precharge MOS transistors, one active pull-up circuit and one sense amplifier are connected with each pair of bit lines.

FIG. 2 is a timing chart for illustrating the read/write operation of the conventional MOS dynamic type RAM as shown in FIG. 1.

With reference to FIG. 2, description is now made on the operation of the circuit as shown in FIG. 1. Referring to FIG. 2, symbol EXTRAS represents an external row address strobe signal, symbols RAS and RAS represent internal row address strobe signals, symbol WL represents potential change of the word line WL, symbol DWL represents potential change of the dummy word line DWL, symbol BL represents potential change of the bit line BL and symbol BL represents potential change of the bit line BL. The internal RAS signal, the precharge signal φp, the sense amplifier activating signal S0 and the active pull-up signal AR are generated from a conventional circuit (not shown) in sequence after generation of the external RAS signal.

It is assumed here that data "1" is written in the memory cell 10 and data "0" is written in the dummy cell 11. As shown in FIG. 2, during when the external RAS signal is at an "H" level, i.e., when the MOS dynamic type RAM is in a non-active cycle, the precharge signal φp is at an "H"level, whereby the MOS transistors 6 and 7 are brought into ON states and the potentials of the pair of bit lines BL and BL are precharged to the precharge voltage VP =(1/2VCC).

Then, the external RAS signal falls at a time t1 and the internal RAS signal rises and the internal RAS signal falls slightly after the same so that the MOS dynamic type RAM enters an active cycle. At the same time, the precharge signal φP falls to complete the operation for precharging the bit lines BL and BL.

Then, a row address signal (not shown) is latched to be supplied to a row decoder (not shown), which in turn decodes the row address signal. WL and DWL rise at a time t2, whereby the word line WL and the dummy word line DWL are selected. As a result, the memory cell data is read on the bit line BL from the memory cell 10 and the dummy cell data is read on the bit line BL from the dummy cell 11, to cause potential difference between the pair of bit lines BL and BL. In order to read/write the memory cell data at the full level, the respective potentials of the word line WL and the dummy word line DWL are raised up to VCC +VTH +α, where VTH represents the threshold voltage of the MOS transistors 4 and 5.

Then, the sense amplifier activating signal S0 rises at a time t3, to start the sensing operation. Namely, the sense amplifier 12 detects the potentials of the pair of bit lines BL and BL, to lower the potential of the lower level bit line BL to the ground potential VSS. The potential of the higher level bit line BL is also slightly lowered at this time.

Then, the active pull-up signal AR rises at a time t4 to drive the active pull-up circuit 13, which in turn pulls up the potential of the higher level bit line BL to the supply potential VCC.

Then, the external RAS signal rises at a time t5, whereby the internal RAS signal falls and the internal RAS signal rises immediately in response thereto. Then the respective potentials of the word line WL and the dummy word line DWL and the sense amplifier activating signal S0 fall and further the active pull-up signal AR falls to complete the pull-up operation.

Then, the precharge signal φP rises to start precharging the potentials of the pair of bit lines BL and BL at the precharge voltage VP (=1/2VCC), so that the MOS dynamic type RAM enters a non-active cycle.

As hereinabove described, the internal RAS signal defines non-active and active cycles of the MOS dynamic type RAM, so that the memory operation is performed in the active cycle. The period during when the external RAS signal is at an "L" level, i.e., the period corresponding to t5 -t1 is called as an active cycle time tAC.

The aforementioned active pull-up operation is generally started immediately upon starting of the sensing operation and ended immediately after rise of the external RAS signal, while the aforementioned active cycle time tAC must be sufficiently long in order to completely pull up the potential of the higher level bit line. Namely, when an active pull-up circuit is employed, the active cycle time tAC must be prolonged by the time required for raising the potential of the higher level bit line to the supply potential VCC in comparison with the case of employing no such active pull-up circuit, leading to a disadvantage in view of the operating speed.

SUMMARY OF THE INVENTION

Briefly stated, provided according to the present invention is a semiconductor memory device which comprises a plurality of pairs of bit lines, a plurality of word lines provided to intersect with the plurality of pairs of bit lines, a plurality of memory cells provided in correspondence to the intersection points between the bit line pairs and the word lines to be connected to the respective bit line pairs and the respective word lines, precharge means provided for each pair of bit lines for precharging the potentials of the bit line pair to a first constant potential, memory cell selection/readout means for selecting a memory cell for reading data by selecting a word line after precharging of the bit line pair by the precharge means and reading the data from the selected memory cell, sense amplifier means provided for each pair of bit lines to detect the potentials of the bit line pair upon reading of the data from the selected memory cell thereby to lower the potential of a lower level one of the pair of bit lines to a second constant potential, means for supplying an external row address strobe signal having a constant duration, delay means for delaying the external row address strobe signal by a prescribed period and an internal row address strobe signal generating means for generating an internal row address strobe signal having a trailing edge obtained by delaying the trailing edge of the external row address strobe signal by a prescribed period in response to the external row address strobe signal and the output from the delay means. The internal row address strobe signal alternately repeatedly defines a non-active cycle of the operation of the precharge means and an active cycle for the operation of the memory cell selection/readout means and the sense amplifier means. The semiconductor memory device further comprises active pull-up means provided for each pair of bit lines for pulling up the potential of the higher level one of the pair of bit lines to a third constant potential from immediately after starting of the operation of the sense amplifier means to the end of the active cycle defined by the internal row address strobe signal.

According to another aspect of the present invention, the first and third constant potentials are at a supply potential level and the second constant potential is at a ground potential level.

According to still another aspect of the present invention, the second constant potential is at a ground potential level and the third constant potential is at a supply potential level, while the first constant potential is at an intermediate potential level between the second and third constant potential.

Accordingly, a principal object of the present invention is to provide a semiconductor memory device provided with active pull-up circuits which can completely pull up potentials of higher level bit lines to a prescribed potential level without prolonging an active cycle time.

A principal advantage of the present invention is that the time for the pull-up operation for the bit lines can be sufficiently secured without delaying the trailing timing of the external row address strobe signal, whereby the operating cycle time of the semiconductor memory device can be rendered fast.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an example of a conventional MOS dynamic type RAM provided with active pull-up circuits;

FIG. 2 is a timing chart for illustrating the operation of the circuit as shown in FIG. 1;

FIG. 3 is a circuit diagram showing an embodiment of the present invention; and

FIG. 4 is a timing chart for illustrating the operation of the embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 3 is a circuit diagram showing a part for generating a RAS precharge wait (RPW) signal and an internal RAS signal forming a semiconductor memory device according to an embodiment of the present invention. Except for the part for generating the RPW signal and the internal RAS signal as shown in FIG. 3, the semiconductor memory device according to the present invention is identical in structure to the conventional semiconductor memory device as shown in FIG. 1, and hence detailed description thereof is omitted.

Description is now made on the structure of the signal generating part as shown in FIG. 3.

Referring to FIG. 3, an external RAS signal is inputted in an input terminal 19, to be supplied to the input of a delay circuit 20 formed by a plurality of inverters and to one input of a NAND circuit 27. The delay circuit 20 delays the supplied external RAS signal by a prescribed period to output the same as the RPW signal, which is supplied to the other input of the NAND circuit 27. The NAND circuit 27 is formed by four MOS transistors 21, 22, 23 and 24 and a capacitor 25. A first electrode of the MOS transistor 21 is connected to a power supply line 26 for supplying a supply potential VCC, and a second electrode thereof is connected to a first electrode of the MOS transistor 22. A second electrode of the MOS transistor 22 is connected to a first electrode of the MOS transistor 23, whose second electrode is grounded. A first electrode and a gate electrode of the MOS transistor 24 are connected to the power supply line 26, while a second electrode thereof is connected to the gate electrode of the MOS transistor 21 and a first electrode of the capacitor 25. A second electrode of the capacitor 25 is connected to the juncture between the second electrode of the MOS transistor 21 and the first electrode of the MOS transistor 22. The gate electrode of the MOS transistor 23 is connected to the input terminal 19 as one input of the NAND circuit 27, while the gate electrode of the MOS transistor 22 is connected to the output of the delay circuit 20 as the other input of the NAND circuit 27. The NAND circuit 27 outputs the internal RAS signal in response to the external RAS signal and the RPW signal. The internal RAS signal defines non-active and active cycles of the semiconductor memory device, and the RPW signal is adapted to delay the fall timing of the internal RAS signal.

FIG. 3 is a timing chart for illustrating the operation of the embodiment of the present invention.

With reference to FIG. 4, description is made on the operation of the embodiment of the present invention. Referring to FIG. 4, the operation up to a time t4 is absolutely identical to that of the conventional MOS dynamic type RAM as shown in FIGS. 1 and 2, while the external RAS signal is terminated at a time t5 before the potential of the bit line BL is completely pulled up. However, since the fall timing of the internal RAS signal is controlled by the RPW signal obtained by delaying the external RAS signal, the internal RAS signal will not immediately fall upon rise of the external RAS signal at the time t5, to be maintained in an "H" state. The internal RAS signal falls only when the RPW signal rises at a time t6 delayed by a prescribed period from the rise of the external RAS signal. All of internal signals such as a precharge signal φp the potentials of a word line DWL, a sense amplifier activating signal S0 and an active pull-up signal AR are controlled-by the internal RAS signal and the internal RAS signal, and hence the operation for pulling up the potential of the bit line BL and rewriting in the memory cell 10 is internally continued even if the external RAS signal rises at the time t5. These operations are completed by the time t6. Thus, in the embodiment as shown in FIGS. 3 and 4, the time for the pull-up operation can be sufficiently prolonged without delaying the rise timing of the external RAS signal, to completely pull up the potential of the bit line to the supply potential VCC. According to the embodiment of the present invention, therefore, the active cycle time tAC can be reduced by t6 -t5 in comparison with the conventional MOS dynamic type RAM as shown in FIGS. 1 and 2.

Although the above embodiment has been described with reference to the case where the precharge voltage is 1/2 of the supply potential VCC, a similar effect can be obtained also in case where the precharge voltage is absolutely equal to the supply voltage VCC.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Patent Citations
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6292429Feb 28, 2000Sep 18, 2001Mitsubishi Denki Kabushiki KaishaSynchronous semiconductor memory device allowing data to be satisfactorily rewritten therein
US6477109Aug 7, 2001Nov 5, 2002Mitsubishi Denki Kabushiki KaishaSynchronous semiconductor memory device allowing data to be satisfactorily rewritten therein
Classifications
U.S. Classification365/189.11, 365/204, 365/193, 365/203
International ClassificationG11C11/4076, G11C11/4094
Cooperative ClassificationG11C11/4076, G11C11/4094
European ClassificationG11C11/4094, G11C11/4076
Legal Events
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