|Publication number||USRE34808 E|
|Application number||US 07/610,603|
|Publication date||Dec 20, 1994|
|Filing date||Nov 8, 1990|
|Priority date||Nov 5, 1986|
|Also published as||DE3789199D1, DE3789199T2, EP0267017A1, EP0267017B1, US4783607|
|Publication number||07610603, 610603, US RE34808 E, US RE34808E, US-E-RE34808, USRE34808 E, USRE34808E|
|Original Assignee||Xilinx, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (19), Non-Patent Citations (6), Referenced by (46), Classifications (13), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Copending U.S. patent application Ser. No. 788,344, filed Sept. 19, 1985 on behalf of H. C. Hsieh and assigned to the same assignee, .Iadd.now U.S. Pat. No. 4,820,937, incorporated herein by reference, .Iaddend.discloses a TTL/CMOS input buffer incorporating an input inverter in the CMOS input buffer. The trigger point of the input inverter is established at a selected level in response to a reference voltage provided by a voltage generator. The circuit realizes a .[.reduce.]. .Iadd.reduced .Iaddend.sensitivity to variations in power supply noise and maximizes input noise margins. The input buffer has high speed, low or no DC power dissipation at TTL input levels, and no DC power dissipation at CMOS input levels.
1. Field of The Invention
This invention relates to a TTL/CMOS compatible input buffer incorporating a Schmitt trigger.
2. Description of The Prior Art
Conventional bipolar integrated circuits operate at low voltage logic levels. Typically, a low or logical "0" for TTL logic circuits ranges from 0.0 to 0.8 volts and a high or logical "1" ranges from 2.0 to 5.0 volts. Thus in order to distinguish between a logical 0 and a logical 1 a CMOS inverter must be capable of switching somewhere between 0.8 and 2.0 volts and preferably at approximately 1.4 volts in order to provide the widest possible noise margin. A CMOS inverter generally operates at voltages of 4.5 to 15 volts with 5 volts being typical. If the source of the P-channel transistor in the CMOS inverter is connected to a voltage of 5 volts, for example, the P-channel transistor will draw a steady state current when a TTL logical "1" as low as 2.0 volts is applied to its gate. Hence it is desirable to establish the switching or trigger point of the CMOS input inverter in a TTL/CMOS buffer at approximately 1.4 volts to maximize noise margins, and to provide a voltage of less than 5 volts on the sources of P-channel transistors in the input buffer in order to reduce steady state power consumption.
To overcome the problem of the differences in operating voltages of the TTL logic circuits and the CMOS circuits, various solutions have been proposed. For example, U.S. Pat. No. 4,471,242 issued Sept. 11, 1984 to Noufer, et al., which is incorporated herein by reference, describes a TTL/CMOS input buffer that accomplished buffering a TTL signal to a CMOS signal with low current flow through a CMOS input inverter in a static (nonswitching) condition. This is achieved by providing a selected reference voltage to the source of the P-channel transistor in the CMOS input inverter. The reference voltage is selected to be less than the lowest voltage level of the TTL logical "1" (2.0 volts) minus the threshold voltage of the P-channel transistor.
Similarly, U.S. Pat. No. 4,475,050 issued to Noufer on Oct. 2, 1984, which is incorporated herein by reference, prevents current flow through the CMOS inverter of the TTL to CMOS input buffer by providing a reference voltage to the source of the P-channel transistor in the input inverter which is responsive to the voltage level of the TTL input signal.
U.S. Pat. No. 4,469,959, issued to Luke et al. on Sept. 4, 1984, which is incorporated herein by reference, describes a bypass means that compensates for the body effect of the load transistor to maintain the switch point of the input inverter stage at a relatively constant value.
When a relatively large number of input buffers are provided in a circuit network, for example as many as 60, if all the inputs are switched simultaneously, the trigger points of the inverters, such as used with the circuit disclosed in the copending patent application, would vary as the reference voltage supplied to the input inverters varies. The greater the number of input buffers that are connected and switched simultaneously, the greater the potential peak-to-peak noise. Simultaneous switching causes a drain on the current source resulting in wiggle of the reference voltage. If the transistion time of an input inverter is slow, such that it intersects with the waveform of the trigger point of the input inverter more than once, the input would be interpreted as having logical level 1010, so that multiple transitions could appear at the output of the input buffer. It would be desirable to reduce the sensitivity to transients and peak-to-peak noise when switching the input stages of the input buffer circuits.
According to this invention, a TTL/CMOS compatible input buffer incorporates a Schmitt trigger in order to reduce sensitivity of the input buffer to noise on the reference voltage and to provide improved tolerance for slow input transitions. The operation of the Schmitt trigger is characterized by hysteresis so that the trigger point is lower when its input voltage is falling than when the input voltage is rising, and the difference in the voltage levels of the trigger points provides improved tolerance to noise and enhances noise immunity. Also, in the circuit of this invention, noise associated with the reference voltage is damped by a large capacitor, and a large transistor provides a true voltage source to limit excursions of the voltage waveform.
The invention will be described in detail with reference to the drawing in which:
FIG. 1 is a schematic block diagram of the novel circuit of this invention;
FIG. 2 includes waveforms depicting an indeterminate output caused by noisy reference voltage and a slow input transition;
FIGS. 3a and 3b represent respectively the transfer curves of a normal inverter and a Schmitt trigger; and
FIG. 4 is a computer simulation of the TTL/CMOS input buffer of this invention when operating with a Schmitt trigger in a noisy reference voltage environment.
With reference to FIG. 1, a TTL/CMOS compatible input buffer comprises a Schmitt trigger 10 and a reference voltage generator 20. The reference voltage generator 20 provides a reference voltage to establish the trigger point of the Schmitt trigger to be at the desired level of approximately 1.4 volts. The Schmitt trigger 10 has a hysteresis characteristic that effectively enhances noise immunity, and is used in the input buffer circuit of this invention to replace the inverter circuit incorporated in the input buffer disclosed in the aforementioned copending patent application.
With reference to FIG. 1, the Schmitt trigger includes a P-channel enhancement transistor M1 and N-channel enhancement transistors M2, M3 and M4. The gate electrodes of transistors M1, M2 and M3 are connected to receive an input signal VIN through lead 13, and the drains of transistors M1 and M2 are connected to the gate of transistor M4 to couple to an output terminal VOUT through lead 16. The source of transistor M1 is connected to the drain of transistor M4 to couple to the reference voltage generator 20 through a lead 21. The drain of transistor M3 is connected to the sources of transistors M2 and M4. The source of transistor M3 is connected to a reference potential or ground.
When the input buffer operates in the TTL mode, i.e., when the signals on input lead VIN of the input buffer are at TTL levels switching between 0.8 volts and 2.0 volts, one desirable voltage level of reference voltage VREF on output lead 21 is approximately 3.5 volts. Thus the DC power loss of the input buffer is substantially reduced from the DC power loss that would result if the reference voltage VREF were at Vcc, which is typically 5 volts. The DC power loss is the power loss resulting from the steady state current that flows from the reference generator 20 through transistors M1, M2 and M3 to ground.
When the Schmitt trigger 10 is in the steady or nonswitching state, it is desirable that the trigger of trip point, which is a function of VREF, should be at or near the midpoint of the TTL voltage levels, which is approximately 1.4 volts. The Schmitt trigger operates at two trigger voltage levels, one trigger occurring at the rising edge of the input signal and the second trigger occurring at the falling edge of the input signal. In accordance with this invention, a larger noise margin is obtained by virtue of the two distinct trigger voltages which are centered about the desired 1.4 volt level.
When operating the input buffer with the Schmitt trigger, as illustrated in FIG. 1, when the input node or terminal T4 is at 0 volts, then mode T2 is charged to the reference voltage VREF and node T3 is charged to VREF -Vt (M4), where Vt (M4) is the threshold voltage of M4, an N-channel enhancement transistor. As the input signal begins to rise, the voltage at node T3 starts to fall. The DC characteristic is determined by transistors M3 and M4, while transistor M2 is off. As the input rises to a voltage level that is Vt (M2) above the voltage at node T3, transistor M2 turns on and the voltage at node T2 falls quickly so that transistor M4 cuts off.
For the falling edge of the input signal, initially both voltages at node T2 and node T3 are 0 volts and transistor M4 is nonconducting or off. As the input VIN applied to node T4 falls, the voltages at node T2 and at node T3 both rise. When the voltage difference between the input VIN and that at terminal T3 is less than the voltage Vt (M2), transistor M2 cuts off and the voltage at terminal T2 rises rapidly to the reference voltage VREF and transistor M4 is turned .[.off.]. .Iadd.on.Iaddend.. The DC characteristic of the Schmitt trigger is then determined by transistors M3 and M4 that provide a higher trigger point than the inverter comprising transistors M1, M2 and M3.
In operation of the input buffer, a power down (PD) control signal is applied to transistor P4 of the reference voltage generator 20. P4 is coupled to a voltage supply Vcc and to ground potential through series resistors R1 and R2. Resistor R1 has a resistance value greater than that of R2, in this implementation, being in the ratio of 5R:2R, by way of example. The resistance values are selected so that the reference voltage at node T1A is at the midpoint of the range of TTL values, .[.taht.]. .Iadd.that .Iaddend.is at 1.4 Volts approximately. When transistor P4 is on, the reference voltage on node T1A is substantially equal to the desired trigger point of the Schmitt trigger 10, which is the selected value between the low level TTL signal (0.8 volts) and the high level TTL signal (2.0 Volts).
The voltage at node T1A is applied to the inverting input lead 26 of operational amplifier 25. Capacitor C1 which is connected between T1A and ground smooths any glitches that may be caused by power supply perturbations. The noninverting input lead 27 of the op amp 25 is connected to the .[.ouptut.]. .Iadd.output .Iaddend.node T2A of the reference input buffer stage 11A of the reference voltage generator. The reference input buffer stage 11A comprises a P-channel transistor P2, an N-channel transistor N2, an N-channel transistor N3, and an N-channel transistor N4. The configuration of the reference input buffer stage 11A is substantially equivalent to that of the Schmitt trigger 10, except that the node T2A is shorted to the gates of P2, N2 and N3. The ratios of the sizes of the transistors P2, N2, N3 and N4 are substantially the same as the ratios of sizes of transistors M1, M2, M3 and M4, respectively. The output signal of the operational amplifier 25 controls the gate of a P-channel transistor P3, which is a relatively large transistor. The transistor P3 acts as a true voltage source and limits excursions of the voltage at node T3A. P3 supplies transient current for all input buffers in the system, which are similar to the Schmitt trigger input buffer 29, and is connected to the output lead 21 of the reference voltage generator 20. A capacitor C2, which is a large capacitor having a capacitance value of 50 picoFarads, by way of example, is connected to output lead 21 of the reference voltage generator 20 and serves to stabilize the reference voltage.
The Schmitt trigger input buffer 29 includes an output stage comprising an inverter formed with a P-channel transistor .[.MR.]. .Iadd.M5 .Iaddend.and N-channel transistor M6. The transistor M5 is a native P-channel transistor having a threshold voltage of about -1.6 Voltsą0.2 Volts, so that the inverter formed by the M5 and M6 transistors does not consume DC power when VREF has a value greater than or equal to 3.5 volts approximately.
Since the voltage on the gates of transistors P2, N2 and N3 is the same as the voltage on node T2A connected to the drains of transistors P2 and N2, the trigger point of the reference input buffer is in effect the voltage at node T2A, which is connected to the noninverting lead 27 at the input of op amp 25. The output signal from the op amp 25 is fed to the gate of P3 to establish a reference voltage at node T3A so that the voltage at the node T2A approaches the desired level of about 1.4 volts.
Since the ratios of the sizes of the transistors of the Schmitt trigger 10 are the same as the ratios of the sizes of the transistors of the reference input buffer stage 11A, and since the node T3A is connected to node T1 of the Schmitt trigger, the trigger point of the Schmitt trigger is the same as the trigger point of the reference input buffer, which is at the desired approximate 1.4 volt level.
FIG. 2 illustrates two waveforms, representing the reference voltage VREF, and the trigger voltage VTRIG with slow input transistions and a noisy reference voltage that produces a indeterminate output signal. A feature of the invention is that the Schmitt trigger input buffer with its hysteresis characteristic overcomes the effect of the slow input transistions. The hysteresis of the Schmitt trigger, which is controlled by the transistor sizes, causes a change in the threshold level of the trigger. The Schmitt trigger is characterized by two trigger points which are higher and lower than the desired 1.4 volt trigger level respectively. The trigger points are switched in response to the rising and falling edges of the input signal VIN. By virtue of the hysteresis of the Schmitt trigger, a significant improvement is realized in noise immunity for noise on the reference voltage and for noise on the input signal.
FIGS. 3a and 3b show the transfer curves for a normal inverter and a Schmitt trigger respectively, illustrating the hysteresis characteristic of the Schmitt trigger.
FIG. 4 represents a computer simulation obtained by simulating the operation of the Schmitt trigger input buffer in a noisy reference voltage environment. The input buffer of this invention affords better noise immunity and improves the tolerance to the noise level of the reference voltage, thereby increasing the reliability of the input buffer even when the input signal has a very slow transition time.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4032795 *||Apr 14, 1976||Jun 28, 1977||Solitron Devices, Inc.||Input buffer|
|US4258272 *||Mar 19, 1979||Mar 24, 1981||National Semiconductor Corporation||TTL to CMOS input buffer circuit|
|US4430582 *||Nov 16, 1981||Feb 7, 1984||National Semiconductor Corporation||Fast CMOS buffer for TTL input levels|
|US4438352 *||Aug 17, 1982||Mar 20, 1984||Xerox Corporation||TTL Compatible CMOS input buffer|
|US4469959 *||Mar 15, 1982||Sep 4, 1984||Motorola, Inc.||Input buffer|
|US4471242 *||Dec 21, 1981||Sep 11, 1984||Motorola, Inc.||TTL to CMOS Input buffer|
|US4472647 *||Aug 20, 1982||Sep 18, 1984||Motorola, Inc.||Circuit for interfacing with both TTL and CMOS voltage levels|
|US4475050 *||May 5, 1983||Oct 2, 1984||Motorola, Inc.||TTL To CMOS input buffer|
|US4490633 *||Dec 28, 1981||Dec 25, 1984||Motorola, Inc.||TTL to CMOS input buffer|
|US4504747 *||Nov 10, 1983||Mar 12, 1985||Motorola, Inc.||Input buffer circuit for receiving multiple level input voltages|
|US4563595 *||Oct 27, 1983||Jan 7, 1986||National Semiconductor Corporation||CMOS Schmitt trigger circuit for TTL logic levels|
|US4584492 *||Aug 6, 1984||Apr 22, 1986||Intel Corporation||Temperature and process stable MOS input buffer|
|US4587447 *||May 4, 1984||May 6, 1986||Siemens Aktiengesellschaft||Input signal level converter for an MOS digital circuit|
|US4612461 *||Feb 9, 1984||Sep 16, 1986||Motorola, Inc.||High speed input buffer having substrate biasing to increase the transistor threshold voltage for level shifting|
|US4820937 *||Sep 19, 1985||Apr 11, 1989||Xilinx, Incorporated||TTL/CMOS compatible input buffer|
|DD227843A1 *||Title not available|
|DE2708021A1 *||Feb 24, 1977||Aug 31, 1978||Eurosil Gmbh||Schaltungsanordnung in integrierter cmos-technik zur regelung der speisespannung fuer integrierte schaltungen|
|EP0154337A2 *||Mar 6, 1985||Sep 11, 1985||Kabushiki Kaisha Toshiba||Transistor circuit for semiconductor device with hysteresis operation and manufacturing method therefor|
|GB2130833A *||Title not available|
|1||B. L. Dokic, "CMOS Schmitt Triggers", IEE Proceedings, vol. 131, Part G, No. 5, Oct. 1984, pp. 197-202, IEE, Old Woking, Surrey, Great Britain.|
|2||*||B. L. Dokic, CMOS Schmitt Triggers , IEE Proceedings, vol. 131, Part G, No. 5, Oct. 1984, pp. 197 202, IEE, Old Woking, Surrey, Great Britain.|
|3||Branko Dokic, "Modified CMOS Inverters", 2218 Microelectronics Journal, vol. 14 (1983) Jul.-Aug., No. 4, Kirkcaldy, Great Britain, pp. 39-44.|
|4||*||Branko Dokic, Modified CMOS Inverters , 2218 Microelectronics Journal, vol. 14 (1983) Jul. Aug., No. 4, Kirkcaldy, Great Britain, pp. 39 44.|
|5||Paul R. Gray and Robert G. Meyers, "Analysis and Design of Analog Integrated Circuits" pp. 741-749, 762, John Wiley & Sons (2nd Ed.) 1984.|
|6||*||Paul R. Gray and Robert G. Meyers, Analysis and Design of Analog Integrated Circuits pp. 741 749, 762, John Wiley & Sons (2nd Ed.) 1984.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5877632 *||Apr 11, 1997||Mar 2, 1999||Xilinx, Inc.||FPGA with a plurality of I/O voltage levels|
|US6204691||May 11, 2000||Mar 20, 2001||Xilinx, Inc.||FPGA with a plurality of input reference voltage levels grouped into sets|
|US6246258||Jun 21, 1999||Jun 12, 2001||Xilinx, Inc.||Realizing analog-to-digital converter on a digital programmable integrated circuit|
|US6294930||Jan 6, 2000||Sep 25, 2001||Xilinx, Inc.||FPGA with a plurality of input reference voltage levels|
|US6335636||May 1, 2001||Jan 1, 2002||Altera Corporation||Programmable logic device input/output circuit configurable as reference voltage input circuit|
|US6346827||Aug 4, 1999||Feb 12, 2002||Altera Corporation||Programmable logic device input/output circuit configurable as reference voltage input circuit|
|US6351145||Apr 6, 2001||Feb 26, 2002||Xilinx, Inc.||Realizing analog-to-digital converter on a digital programmable integrated circuit|
|US6433579||May 22, 2001||Aug 13, 2002||Altera Corporation||Programmable logic integrated circuit devices with differential signaling capabilities|
|US6448809||Aug 7, 2001||Sep 10, 2002||Xilinx, Inc.||FPGA with a plurality of input reference voltage levels|
|US6472903||Aug 4, 1999||Oct 29, 2002||Altera Corporation||Programmable logic device input/output architecture with power bus segmentation for multiple I/O standards|
|US6489826 *||Oct 5, 2001||Dec 3, 2002||Seiko Epson Corporation||Clock generator with programmable non-overlapping clock-edge capability|
|US6653881||Oct 23, 2002||Nov 25, 2003||Seiko Epson Corporation||Clock generator with programmable non-overlapping-clock-edge capability|
|US6714050||Jul 3, 2001||Mar 30, 2004||Altera Corporation||I/O cell configuration for multiple I/O standards|
|US6831480||Jan 7, 2003||Dec 14, 2004||Altera Corporation||Programmable logic device multispeed I/O circuitry|
|US6836151||Feb 17, 2004||Dec 28, 2004||Altera Corporation||I/O cell configuration for multiple I/O standards|
|US6900682||Sep 25, 2003||May 31, 2005||Seiko Epson Corporation||Clock generator with programmable non-overlapping-clock-edge capability|
|US6911860||Nov 9, 2001||Jun 28, 2005||Altera Corporation||On/off reference voltage switch for multiple I/O standards|
|US6940302||Jan 7, 2003||Sep 6, 2005||Altera Corporation||Integrated circuit output driver circuitry with programmable preemphasis|
|US6958679||Feb 5, 2004||Oct 25, 2005||Xilinx, Inc.||Binary hysteresis equal comparator circuits and methods|
|US6965251||Feb 18, 2004||Nov 15, 2005||Altera Corporation||Input buffer with hysteresis option|
|US7023238||Jan 7, 2004||Apr 4, 2006||Altera Corporation||Input buffer with selectable threshold and hysteresis option|
|US7034570||Dec 3, 2004||Apr 25, 2006||Altera Corporation||I/O cell configuration for multiple I/O standards|
|US7053687||Feb 5, 2004||May 30, 2006||Xilinx, Inc.||Binary hysteresis comparator circuits and methods|
|US7109743||Jun 7, 2005||Sep 19, 2006||Altera Corporation||Integrated circuit output driver circuitry with programmable preemphasis|
|US7265587||Jul 26, 2005||Sep 4, 2007||Altera Corporation||LVDS output buffer pre-emphasis methods and apparatus|
|US7307446||Aug 24, 2006||Dec 11, 2007||Altera Corporation||Integrated circuit output driver circuitry with programmable preemphasis|
|US7352222||Apr 22, 2005||Apr 1, 2008||Seiko Epson Corporation||Clock generator with programmable non-overlapping-clock-edge capability|
|US7365570||May 25, 2005||Apr 29, 2008||Micron Technology, Inc.||Pseudo-differential output driver with high immunity to noise and jitter|
|US7598779||Oct 8, 2004||Oct 6, 2009||Altera Corporation||Dual-mode LVDS/CML transmitter methods and apparatus|
|US7622957||Feb 21, 2008||Nov 24, 2009||Micron Technology, Inc.||Pseudo-differential output driver with high immunity to noise and jitter|
|US7642832||Jan 22, 2008||Jan 5, 2010||Seiko Epson Corporation||Clock generator with programmable non-overlapping-clock-edge capability|
|US7733118||Mar 6, 2008||Jun 8, 2010||Micron Technology, Inc.||Devices and methods for driving a signal off an integrated circuit|
|US7868658||Jan 7, 2009||Jan 11, 2011||Marvell International Ltd.||Level shifter circuits and methods for maintaining duty cycle|
|US7953162 *||Nov 17, 2006||May 31, 2011||Intersil Americas Inc.||Use of differential pair as single-ended data paths to transport low speed data|
|US8175173 *||Apr 20, 2011||May 8, 2012||Intersil Americas Inc.||Methods and systems for transmitting signals differentially and single-endedly across a pair of wires|
|US8183880||May 4, 2010||May 22, 2012||Micron Technology, Inc.||Devices and methods for driving a signal off an integrated circuit|
|US20040056699 *||Sep 25, 2003||Mar 25, 2004||Seiko Epson Corporation||Clock generator with programmable non-overlapping-clock-edge capability|
|US20050151564 *||Dec 3, 2004||Jul 14, 2005||Altera Corporation||I/O cell configuration for multiple I/O standards|
|US20050189978 *||Apr 22, 2005||Sep 1, 2005||Seiko Epson Corporation||Clock generator with programmable non-overlapping-clock-edge capability|
|US20050237082 *||Jun 7, 2005||Oct 27, 2005||Altera Corporation||Integrated circuit output driver circuitry with programmable preemphasis|
|US20060267633 *||May 25, 2005||Nov 30, 2006||Micron Technology, Inc.||Pseudo-differential output driver with high immunity to noise and jitter|
|US20080129360 *||Jan 22, 2008||Jun 5, 2008||Seiko Epson Corporation||Clock Generator With Programmable Non-Overlapping-Clock-Edge Capability|
|US20080211535 *||Feb 21, 2008||Sep 4, 2008||Micron Technology, Inc.||Pseudo-differential output driver with high immunity to noise and jitter|
|US20090224802 *||Mar 6, 2008||Sep 10, 2009||Micron Technology, Inc.||Devices and methods for driving a signal off an integrated circuit|
|US20100213972 *||May 4, 2010||Aug 26, 2010||Micron Technology, Inc.||Devices and methods for driving a signal off an integrated circuit|
|USRE40011||Oct 19, 2001||Jan 22, 2008||Altera Corporation||System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly|
|U.S. Classification||326/71, 326/24, 327/206|
|International Classification||H03K19/003, H03K19/0185, H03K3/353, H03K3/3565|
|Cooperative Classification||H03K3/3565, H03K19/00361, H03K19/018521|
|European Classification||H03K19/003J4, H03K19/0185B4, H03K3/3565|
|Nov 13, 1995||FPAY||Fee payment|
Year of fee payment: 8
|Mar 13, 2000||FPAY||Fee payment|
Year of fee payment: 12
|May 12, 2010||AS||Assignment|
Effective date: 19861105
Owner name: XILINX, INC.,CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HSIEH, HUNG-CHENG;REEL/FRAME:024369/0669