US RE35296 E Abstract Apparatus for determining the number of cycles occurring in a frequency modulated signal during a sample period, including not only the number of full cycles but any portion of a cycle, by determining the number of whole cycles and adding to this a value obtained by counting the number of high frequency clock cycles occurring between the time of the last rising edge of a full cycle and the end of the sample period, and the number of high frequency clock cycles occurring from the last rising edge prior to the start of the sample period and the start of the sample period and the number of high frequency clock cycles in a whole cycle.
Claims(12) 1. Apparatus for determining the number of full cycles and any fraction of a cycle N
_{t} in an output signal F_{1} during a sample period, the signal F_{1} consisting of a plurality of cycles and each cycle having a leading edge comprising:clock means producing a high frequency clock pulse; and counting means operable to count the number LE, of leading edge occurrences during the sample period, to count the number of clock cycles N _{n-1}, occurring between the last leading edge occurrence prior to the start of the sample period and the start of the sample period, to count the number of clock cycles N_{n}, occurring between the last leading edge occurrence prior to the end of sample period and the end of the sample period, .[.and.]. .Iadd.the counting means including means .Iaddend.to count .[.the.]. .Iadd.a first.Iaddend.number of clock cycles, .[.D.]. .Iadd.D_{n-1}, occurring in the period between two consecutive leading edges .Iadd.just prior to the start of the sample period and to count a second number of clock cycles, D_{n}, occurring in the period just prior to the end of the sample period, .Iaddend.and producing an output indicative of N_{t} in accordance with the equationN =LE+N
_{n} /D_{n} -N_{n-1} /D_{n-1}..]. 3. Apparatus according to claim 1 wherein the counting means includes means to store the number LE_{n-1} of leading edge occurrences in F_{1} at the start of the sample period and the number LE_{n} of leading edge occurrences in F_{1} at the end of the sample period with LE being determined by LE
_{n} -LE_{n-1}. 4. Apparatus according to claim 1 further including means to generate a first pulse to mark the start of the sample period and a second pulse to mark the end of the sample period. 5. Apparatus according to claim 1 wherein the signal F
_{1} is an output of a digital accelerometer having a sensing axis and N_{t} is indicative of the incremental change in velocity along the sensing axis. 6. Apparatus according to claim 5 wherein the digital accelerometer has a second output F
_{2} and further including apparatus for determining the number of full cycles and any fraction of a cycle N'_{t} in F_{2} during the sample period, the signal F_{2} consisting of a plurality of cycles with each cycle having a leading edge and the counting means is operable to count the number LE', of leading edge occurrences during the sample period, to count the number of clock cycles N'_{n-1}, occurring between the last leading edge occurrence prior to the start of the sample period and the start of the sample period, to count the number of clock cycles N'_{n}, occurring between the last leading edge occurrence prior to the end of sample period and the end of the sample period, counting the number of clock cycles D', between two consecutive leading edges and producing an output indicative of N'_{t} in accordance with the equation N'_{t} =LE'+N'
_{n} /D'-N'_{n-1} /D'. 7. Apparatus according to claim 6 wherein the counting means includes means to count a first D' value D'_{n-1}, just prior to the start of the sample period and a second D' value D'_{n}, just prior to the end of the sample period and the output indicative of N'_{t} is in accordance with the equationN'
_{t} =LE'+N'_{n} /D'_{n} -N'_{n-1} /D'_{n-1}. 8. Apparatus according to claim 6 wherein the counting means includes means to store the number LE'_{n-1} of leading edge occurrences in F_{2} at the start of the sample period and the number LE'_{n} of leading edge occurrences in F_{2} at the end of the sample period with LE' being determined by LE'
_{n} -LE'_{n-1}. 9. Apparatus according to claim 6 further including processor means connected to receive the outputs indicative of N_{t} and N'_{t} and operable to produce a resultant output indicative of the incremental change in velocity along the sensing axis. 10. Apparatus according to claim 9, further including circuit means receiving an output signal F
_{T} which varies in frequency with temperature and operable to produce a signal LE_{T} to the processor so as to modify the calculation of incremental velocity along the sensing axis as a function of temperature. 11. Apparatus according to claim 10 wherein the signal F
_{T} is a plurality of cycles and the circuit means includes counting means to count the number of cycles in F_{T} during the sample period to produce LE
_{T}. 12. The method of determining the number of cycles and portions of a cycle N_{t} in a signal F_{1} during a sample period with each cycle having a leading edge comprising the steps of:A) producing first and second strobe pulses to define a sample period; B) producing a plurality of clock cycles during the sample period; C) counting the number of leading edge occurrences LE in F _{1} during the sample period;D) counting the number of clock cycles N _{n-1} between the last leading edge in F_{1} prior to the start of the sample period and the first strobe pulse;E) counting the number of clock cycles N _{n} between the last leading edge in F_{1} prior to the end of the sample period and the second strobe pulse;F1) counting the number of clock cycles .[.D during two consecutive.]. .Iadd.D _{n-1} occurring between the last two .Iaddend.leading edges in F_{1} .Iadd.prior to the start of the sample period;F2) counting the number of clock cycles D _{n} occurring between the last two leading edges in F_{1} prior to the end of the sample period.Iaddend., andG) solving for N _{t} according to the equationN F1) counting the number of clock cycles D _{n-1} occurring between the last two leading edges in F_{1} prior to the start of the sample period;F2) counting the number of clock cycles D _{n} occurring between the last two leading edges in F_{1} prior to the end of the sample period, and wherein step G) solves for N_{t} for F_{1} according to the equationN
_{t} =LE+N_{n} /D_{n} -N_{n-1} /D_{n-1}..]. 14. The method of claim 12, wherein step C includes the further step of:C1) storing the number LE _{n-1} of leading edge occurrences in F_{1} at the start of the sample period,C2) storing the number LE _{n} of leading edge occurrences in F_{1} at the end of the sample period andC3) producing LE in accordance with the equation LE=LE Description The present invention relates to a method and apparatus for accurately counting the number of cycles and partial cycles occurring in a frequency modulated electrical signal during a sample period. More particularly the invention relates to a method and apparatus for determining the incremental change in velocity experienced by the accelerometer by counting cycles in two outputs of a digital accelerometer during a sample period. In the art of sensing acceleration, a type of accelerometer described by a Peters U.S. Pat. No. 4,712,427 operates to produce four digital outputs. Two of these outputs are in the form of acceleration dependent frequency modulated signals. The other two outputs provide information concerning temperature and calibration coefficients respectively. To calculate the incremental change in velocity being experienced one may determine the changes in frequency between the first two outputs and provide adjustments in accordance with the second two outputs. Determining frequency changes is sometimes accomplished by means of a counter which counts the number of cycles of each output during a sample period. To obtain high accuracy, it is not only necessary to count the number of full cycles during a sample period but also any portions of a cycle which occur during that period. Having the number of full and partial cycles of the two acceleration dependent frequency modulated outputs, the average frequency during the sample period may then be numerically converted by a system processor to calculate the incremental velocity along the sensing axis of the accelerometer. A full and partial cycle counting apparatus has been described in the Hulsing II, et al U.S. Pat. No. 4,786,861 which employs a first counter operable to provide an output count indicative of the number of full cycles in a sampling period defined by two successive strobe signals, a second counter which counts the integer number of high frequency clock cycles occurring during a full cycle of the unknown frequency and a third counter which counts the integer number of high frequency clock cycles during a time period starting with the end of the sample period and ending with the next rising edge of the signal being measured. Subtracting the ratio of the number of high frequency clock cycles during this latter time period to the number of high frequency counts during a full cycle from 1 is indicative of the portion of a full cycle that occurs before the end of the sample period. The ratio defined above indicates the portion of a full cycle that occurs after the start of the next sample period. A problem encountered in the above described apparatus, arises from the fact that it is necessary to wait until after the end of a sample period to determine the number of high frequency clock periods existing in a portion of a cycle of the signal being measured. As a result, the information used to determine the incremental change in velocity along the sensing axis cannot be sent to the system processor for use until after the completion of the full cycle of the unknown frequency which was initiated prior to the end of the subsequent sample period. The present invention provides an apparatus and method for determining the number of full and partial cycles occurring during a sample period of a frequency modulated digital electric signal and obtains this information during the sample period so that it may be sent to the system processor immediately after the start of the next sample period. FIG. 1 shows a block diagram of the system involving the digital accelerometer, the application specific integrated circuit (ASIC) which contains the counting apparatus of the present invention and, the system processor; FIG. 2 is a timing diagram showing the relationship between one of the outputs of the digital accelerometer, the high frequency clock and the asynchronous strobe input defining a sample period; and, FIG. 3 is a block schematic diagram of the apparatus for accurately counting the quantity of full and partial cycles occurring during a sample period in the outputs of the digital accelerometer. In FIG. 1 a digital accelerometer 10 which may be of the type shown in the above referred U.S. Pat. No. 4,712,427 is shown producing 4 outputs, F The output F A strobe input 22 is shown producing a signal to ASIC 14 via a line 24 and the strobe signal comprises a series of periodic pulses used to determine a sample period for finding the frequency variations of the signals F ASIC 14 contains circuitry which will be described in connection with FIG. 3 to produce a plurality of outputs on a line 28 which are presented to a system processor 30. The signals on line 28 will be serial or parallel data signals indicative of the various outputs produced by the circuitry of FIG. 3 an the system processor 30 will operate on the signals to produce and output on a line 32 indicative of the incremental change in velocity being experienced by the digital accelerometer 10 along the sensing axis. Referring to FIG. 2, one of the outputs, F It will be apparent that the total number of cycles of the accelerometer output signal 40 occurring between lines 50 and 52 (the sample period) will be given by the number of full cycles occurring during this period and adding to that the portion represented by N This value is obtained by a first counter in FIG. 3 which receives the acceterometer output signal 40 of FIG. 2 and continuously counts the number of leading edges, LE, that occur where each leading edge of accelerometer output signal 40 is a rising edge of signal 40. The output value of the LE counter, at the end of each sample period is sent to the system processor. The system processor uses the output value of the leading edge counter at the completion of the previous sample period (LE
NT=(LE This expression can be simplified to:
NT FIG. 3 shows a circuit operable to count the various full and partial cycles present in the two frequency modulated acceleration dependent outputs of the digital accelerometer in order to arrive at the values suitable for the system processor to solve equation 2. Turning now to FIG. 3 a pulse accumulator enclosed by dash lines 70 is shown receiving a first input from a box 72 labeled F An enable circuit box 100 is shown in FIG. 3 receiving an input from strobe 88 via line 90 and a line 101. The enable circuit 100 operates to produce a plurality of separate outputs E A disenable box 110 is shown in FIG. 3 receiving an input E Referring now to the interior of the pulse accumulator 70, a synchronizer box 120 is shown receiving the first frequency F The enable circuit 100 which receives an input from the strobe 88 over lines 90 and 101 operates to produce the output E The synchronized output F The synchronized output F The signal on line 180 is presented to an inverter 182 to provide an output on line 184 to a D store box 186 which also receives the output from the leading edge counter 160 via lines 162 and a line 190. The D store box 186 like the leading edge store and the N store boxes above described contains 16 D-flip flops which follow the output from the leading edge counter 160 so as to store the information indicative of the number of high frequency clock cycles occurring since the last leading edge in the synchronized signal F It is thus seen that serial outputs on line 150, 168, and 194 are presented to the system processor in a way that do not overlap by virtue of the timing of the E In the middle of FIG. 3 a second pulse accumulator is shown by dash lines 200. Pulse accumulator 200 is the same as pulse accumulator 70 and receives the same reset signals on lines 202, 203, and 204 as was received by the pulse accumulator 70. Pulse accumulator 200 also receives a second frequency input from box 210 via an input line 212 to provide the pulse accumulator 200 with a second frequency input signal, F It is thus seen that the two pulse accumulators 70 and 200 of FIG. 3 provide the necessary information for the system processor 30 of FIG. 1 to solve equation 2 for both F Finally in FIG. 3 a system for determining the number of full cycles in a frequency modulated signal indicative of the temperature of the digital accelerometer is shown comprising a third pulse accumulator shown by dash lines 240 receiving an input from the source of the frequency modulated signal indicative of temperature box 242 whose output is on a line 244. Box 242 on line 244 corresponds to the output F
N By calculating N It is therefore seen that I have provided a counting circuit operable to provide information indicative of the number of complete cycles and portions of a cycle existing in a signal in a way which cause the information to be transmitted to a system processor. Many variations will occur to those skilled in the art and I do not wish to be limited to the specific disclosures included herein but we shall only be limited by the following claims. Patent Citations
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