|Publication number||USRE35745 E|
|Application number||US 08/395,135|
|Publication date||Mar 17, 1998|
|Filing date||Feb 27, 1995|
|Priority date||Oct 28, 1988|
|Publication number||08395135, 395135, US RE35745 E, US RE35745E, US-E-RE35745, USRE35745 E, USRE35745E|
|Inventors||Andrea Barsanti, Claudio Diazzi, Fabio Vio|
|Original Assignee||Sgs-Thomson Microelectronics S.R.L.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Referenced by (2), Classifications (6), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
.Iadd.This reissue application is a continuation of application Ser. No. 08/289,489, filed Aug. 11, 1994, now abandoned, which was a reissue application of U.S. Pat. No. 5,138,200, issued on Aug. 11, 1992. .Iaddend.
The present invention relates to a device for generating reference voltage for a switching circuit including a driving block controlled by an input switching signal and a capacitive bootstrap circuit, in particular for an output stage.
As is known, transistors implemented in MOS technology are often used to manufacture output stage circuits. Such output stages comprise N-channel MOS transistors which are driven by a high supply voltage, the drain of said transistors being connected to a positive supply line.
It is also known that a problem which occurs with such outut stages is that of ensuring a correct driving voltage for the gate electrode of the MOS transistors, so as to ensure the operation of the device as a low-resistance switch (with a gate-source voltage VGS above 10 V).
To this end, a capacitive bootstrap circuit is provided. An example of a prior art applied to a half-bridge is shown in FIG. 1; said circuit comprises capacitive bootstrap circuitry and output stage circuitry, the output stage being driven so as to generate a periodic wave-form signal VOUT which oscillates between a low voltage, which is about 0 V in the example being considered, and a high voltage substantially equal to a firsst supply voltage VCC.
In particular, two output transistors T1 and T2 are provided in order to generate the periodic wave-form signal and are driven by two driving elements DR.
According to the input signal VIN, said two transistors T1 and T2 are alternately switched in the ON and OFF state so that the output signal switches between the low voltage of 0 V and the high voltage VCC.
The bootstrap circuitry substantially comprises two elements, i.e. the bootstrap capacitor CB and the bootstrap diode DB. When the transistor T1 is off and the transistor T2 is on, VOUT is connected to the ground and therefore is in the LOW state.
In this condition, the bootstrap capacitor CB is charged through the bootstrap diode DB at a voltage equal to the difference between a second supply voltage, for example 12 V, and the voltage drop across the bootstrap diode DB.
In the reverse condition, i.e. with the transistor T1 in the ON state and the transistor T2 in the OFF state, the potential of the source electrode of the transistor T1 rises toward the value of the first reference voltage VCC, and the bootstrap capacitor maintains the supply to the driving elements DR at about VCC +12 V.
As can be seen, in this stage the bootstrap diode is reverse, biased, and its reverse biasing voltage is equal to the first supply voltage (VCC), thus decoupling the bootstrap capacitor from the second supply voltage.
The problem which arises in the above described circuit is that of satisfying two contrasting requirements.
In fact, an output signal having a good dynamic behavior (i.e. considerable amplitude) is required on one hand, while on the other hand it may be possible to integrate the bootstrap diode.
In order to satisfy the first of the above mentioned requirements, the bootstrap diode DB must have a high breakdown voltage, since, as said, when the output voltage VOUT is high, the diode DB has applied thereto a reverse biasing voltage which is equal to the first reference voltage VCC. This condition is troublesome (in view of the required integration) when the required breakdown voltage of the diode is in the range of hundreds of volts.
On the other hands, in the direct biasing state, the bootstrap diode must have low losses toward the substrate. This is a problem when the diode is implemented by a base to collector junction in order to have high breakdown: in fact in this case the diode is associated with a parasitic vertical PNP transistor.
Therefore the problem arises that it is difficult to integrate a small size diode with a high breakdown and low current losses toward the substrate, and this problem becomes the bigger, the higher is the supply voltage VCC.
Therefore, the aim of the present invention is to provide a device for generating a reference voltage for a bootstrap circuit, in particular for an output stage, which allows said output stage to generate and supply at the output a high-amplitude voltage signal.
Within this aim, a particular object of the present invention is to provide a device which can be easily integrated and can be manufactured with conventional technologies, i.e. bipolar or MOS technology.
Another object of the present invention is to provide a device for generating a reference voltage for the bootstrap circuit which is able to eliminate the problems associated with a high breakdown voltage and affecting the prior art.
Not least object of the present invention is to provide an integrated device producible with conventional methods, as mentioned above, can be obtained at a cost which is relatively low and in any case comparable to that of known similar circuits.
The above described aim and objects, as well as others which may become apparent hereinafter, are achieved by a device for generating a reference voltage for a bootstrap circuit having the features of the characterizing part of claim 1.
The characteristics and advantages of the invention will become apparent from the following detailed description of a preferred but not exclusive embodiment of the present invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein:
FIG. 1 is a circuit diagram of an output stage with a prior art bootstrap circuit;
FIGS. 2 is a block diagram of the output stage and of the bootstrap circuit according to the teachings of the present invention; and
FIG. 3 is a circuit diagram of an embodiment of the present invention, implemented in MOS technology.
FIG. 4 is a circuit diagram of a further embodiment of the present invention, implemented in bipolar technology.
With specific reference to FIG. 2, the output stage comprises a driving block 1, a reference voltage generating block 2 and a bootstrap circuit 3.
In particular, the driving block 1 has an input IN receiving a switching input signal VIN, having for example a square wave-form, and an output OUT supplying output voltage VOUT.
Said input switching signal is sent to the input of a driving element DR2 and the same switching signal is also sent to a further driving element DR1 after being inverted by an inverter element indicated at N.
The outputs of the driving elements are applied to the gate electrodes of first switching transistors M1 and a second switching transistor M2; more specifically, the output of the driving element DR2 is applied to the gate electrode of the switching transistor M1 while the output of the driving element DR1 is applied to the gate electrode of the first switching transistor M1.
As is apparent, the switching transistors illustrated in FIG. 1 are manufactured with MOS technology, but this must not be regarded as a limitation, since said transistors may naturally be manufactured according to any other conventional technology.
As can be seen, the source electrode of the first transistor M1 is connected to the drain electrode of the second transistor M2 so as to supply said output OUT, while the source electrode of the second transistor M2 is connected to the ground and the drain electrode of the transistor M1 is connected to a first supply voltage indicated at VCC.
The output signal VOUT is feedback to said reference voltage block 2 and said bootstrap circuit 3; said reference voltage block 2 is also connected to the first supply voltage line VCC and feeds a reference voltage VFL to the bootstrap diode DBOOT and to be bootstrap capacitor CBOOT.
According to the invention, reference voltage VFL is floating and referred to the output voltage VOUT, and more precisely VFL follows the output voltage VOUT so as to have a convenient charging level for the bootstrap capacitor CBOOT when the output is low (near 0 V) and to have a high level (about VCC) when the output is high. Therefore, when the output is low, the bootstrap capacitor can be charged at the desired level, while when the output is high, the voltage drop across the bootstrap diode DBOOT is low. Therefore, this diode may be easily integrated with low losses (e.g. by the emitter to base junction), while allowing the output stage to supply an output signal having high dynamics.
FIGS. 3 illustrates in detail a possible implementation of the reference voltage generating block 2.
As illustrated, said block comprises two Zener diodes, more specifically a first zener diode DZ1 and a second Zener diode DZ2, having respective Zener voltages VZ1 and VZ2 ; said Zener diodes are mutually connected in series, with the anode of the diode second Zener diode DZ2 being connected to the output OUT and the cathode thereof being connected to the anode of the first Zener diode DZ1.
Said circuit furthermore comprises a third transistor M3 preferably of the MOS type, the drain electrode whereof is connected to the first supply voltage line VCC ; its gate electrode is connected to the cathode of the first Zener diode DZ1 and its source electrode is connected to the output OUT through a resistor R2.
As can be seen, a further resistor R1 is interposed between the gate electrode of the third transistor M3 and the first supply voltage line VCC.
The source electrode S of the transistor M3 is also connected to the anode of the bootstrap diode DBOOT, to supply the floating reference voltage VFL, which, as said, is referred to the output.
In fact, when the input signal VIN causes the second transistor M2 to switch on, the first transistor M1 is off. The output voltage VOUT is low, since the point OUT is connected to the ground, and the bootstrap capacitor CBOOT is charged, through the bootstrap diode, to the voltage level of the source electrode of the third transistor M3, i.e. to the value VFL which is now equal to VZ1 +VZ2 -VGS (VGS being the gate-source voltage of the third transistor M3 which is on in this operating mode).
By appropriately selecting the Zener diodes, the voltage VFL may be in the range of 12 V, like the second supply voltage, as is known in the art.
Thus, the bootstrap capacitor charges at a voltage which is equal to the floating voltage VFL.
Vice versa, when the input signal VIN causes the second transistor M2 to switch off and the first transistor M1 on, the potential of the output OUT starts to rise toward the value of the first reference voltage line VCC, and the bootstrap capacitor maintains a constant voltage equal to the previous value of the floating voltage VFL so as to increase the supply of the driving elements.
Since the floating voltage VFL is always related to the output voltage VOUT, until said output voltage VOUT remains lower than the first reference voltage VCC, the bootstrap diode is directly biased, and the problem of breakdown cannot therefore occur.
Vice versa, when the output voltage VOUT reaches a value proximate to that of the reference voltage VCC, the third transistor M3 switches off, since the voltage across its drain and source electrodes becomes substantially equal to 0 V.
In this condition, the anode of the bootstrap diode is connected through R2 to the output voltage VOUT and is thus reversely biased; but the reverse voltage across said diode is now equal to 12 V, thus avoiding the problems due to the high breakdown voltage which are characteristic of the prior art.
As is evident from the preceding description, the invention fully achieves the intended aim and objects.
A circuit structure has in fact been provided which has, on one hand, no problems in integration, since the voltage between the anode and the cathode of the bootstrap diode during the diode reverse-biasing is low, and has, on the other hand, an output voltage with a high maximum or peak value, since value is equal to the first supply voltage VCC.
Therefore, the diode is not required to have a high breakdown voltage and thus may be implemented by the emitter-base junction, which has no vertical PNP parasitic transistors associated therewith.
The invention as described is susceptible to numerous modifications and variations, all of which are within the scope of the inventive concept.
In particular, the fact is stressed that though the described circuit structure has been implemented in MOS technology, the MOS transistors may naturally be replaced with bipolar transistors, for example of the NPN type. FIG. 4 illustrates the above-mentioned bipolar implementation of the circuit shown in FIG. 3. All circuital elements of FIG. 4 are identical to those of FIG. 3 and are designated by the same reference signs, except for the three MOS transistor M1, M2 and M3 which are here replaced by respective bipolar NPN-type transistors designated by N1, N2 and N3. The bipolar circuit works in an analogous manner to the circuit of FIG. 3. Furthermore, though the circuit as described is intended to be used in an output stage, the invention may be applied to any circuitry with similar problems.
The described resistors may also be replaced with controlled current sources.
In addition, all the details may be replaced with other technically equivalent ones.
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|U.S. Classification||326/88, 327/541, 327/589|
|Jun 22, 1995||AS||Assignment|
Owner name: SGS-THOMSON MICROELECTRONICS, S.R.1., ITALY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:VIO, FABIO;REEL/FRAME:007571/0462
Effective date: 19950529
Owner name: SGS-THOMSON MICROELECTRONICS, S.R.L., ITALY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DIAZZI, CLAUDIO;REEL/FRAME:007571/0365
Effective date: 19950505
Owner name: SGS-THOMSON MICROELECTRONICS, S.R.L., ITALY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BARSANTI, ANDREA;REEL/FRAME:007571/0421
Effective date: 19950602
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Year of fee payment: 8
|Jan 8, 2004||FPAY||Fee payment|
Year of fee payment: 12