|Publication number||USRE35828 E|
|Application number||US 08/628,496|
|Publication date||Jun 23, 1998|
|Filing date||Apr 5, 1996|
|Priority date||Feb 5, 1993|
|Also published as||US5301159|
|Publication number||08628496, 628496, US RE35828 E, US RE35828E, US-E-RE35828, USRE35828 E, USRE35828E|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (1), Classifications (10), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to the field of integrated electronic circuit technology. More particularly, the invention relates to a reliable anti-fuse element to be used in integrated circuits.
Integrated electronic circuits are usually made with all internal connections set during the manufacturing process. However, because of high development costs, long lead times and high manufacturing tooling costs of such circuits, users often desire circuits which can be configured or programmed in the field. Such circuits are called field programmable circuits and they can contain programmable links. Programmable links are electrical interconnects which are either broken or created at selected electronic nodes by the user after the integrated device has been fabricated and packaged in order to activate or deactivate the selected electronic nodes.
Programmable links have been used extensively in programmable read only memory (PROM) devices. Probably the most common form of programmable link is a fusible link. When a user receives a PROM device from a manufacturer, it usually consists of an X-Y matrix or lattice of conductors or semiconductors. At each cross-over point of the lattice a conducting link, call a fusible link, connects a transistor or other electronic node to this lattice network. The PROM is programmed by blowing the fusible links to selected nodes an creating an open circuit. The combination of blown and unblown links represents a digital bit pattern of ones and zeros signifying data which the user wishes to store in the PROM. By providing an address the data stored on a node may be retrieved during a read operation.
In recent years, a second type of programmable link, call an anti-fuse link, has been developed for use in integrated circuit applications. Instead of the programming mechanism causing an open circuit as in the case with fusible links, the programming mechanism in an anti-fuse circuit creates a short circuit or relatively low resistance link. Thus the anti-fuse link presents an open circuit prior to programming and a low resistance connection after programming. Anti-fuse links consist of two electrodes comprised of conductive and/or semiconductive materials and having some kind of a dielectric or insulating material between them. During programming, the dielectric at selected points in between the conductive materials is broken down by predetermined applied voltages, thereby electrically connecting the conducting and/or semiconducting materials together.
A plurality of such anti-fuses may be disposed in a semiconductor integrated circuit, and may be selectively blown to create low impedance interconnects at selected locations within the integrated circuit. The anti-fuses may be blown either before or after packaging of the integrated circuit die.
Critical issues facing the designer of the anti-fuse device is the capability to program the device using a low potential while minimizing leakage currents. The two basic circuit configurations for the anti-fuse element are shown in FIGS. 1 and 2. In both configurations a transistor is serially connected to the anti-fuse element. In the configuration shown in FIG. 1, the anti-fuse 5 is connected to a reference potential and the transistor 10 is connected to a supply potential. There is a transistor source bias associated with this approach which requires a higher supply potential than would be required if there were no transistor source bias. In the configuration shown in FIG. 2, the anti-fuse 15 is connected to a supply potential and the transistor 20 is connected to a reference potential. The circuit of FIG. 2 is much easier to program than the circuit of FIG. 1 due to the elimination of the transistor source bias associated with the approach depicted in FIG. 1. Elimination of the source bias allows the anti-fuse element to be programmed using a lower potential. However, it has been observed that leakage current is increased between the supply potential at supply node 25 and the reference potential at reference node 30, and/or that leakage current is increased between supply node 25 and the substrate. This leakage is not desirable in the programmable circuit for it increases the standby current.
Post program transistor current-voltage curves are shown in FIG. 3. The drain voltage has been increased from 0 V to 5 V in 1 volt increments with the resultant drain current measured and plotted at each increment. The solid lines represent the data plotted for FIG. 2 and the dashed lines represent the data plotted for FIG. 1. The curves have been lettered. The solid lines are represented by a letter having no prime symbol and the dashed lines are represented by a letter having a prime signal. Each of the curves having corresponding letters have the same gate voltage. For example F and F' had a gate voltage of 0 V. It can be clearly seen that when the supply node 25 is the drain of the transistor, as shown in FIG. 2, the leakage current for Vg =0 is too large for the transistor to handle, see curve F. Conversely, if we were to use reference node 35 as the transistor source and the supply node 40 as the transistor drain, as shown in FIG. 1, the transistor leakage at Vg =0 is much lower, see curve F'. However as was discussed earlier, the configuration of FIG. 1 has a transistor source bias which requires a higher supply potential than the circuit of FIG. 2. Therefore a need exists to minimize leakage current while providing a low programming potential.
The object of the invention is to provide a low programming potential while reducing leakage current. The invention features a circuit wherein a serially connected transistor and anti-fuse element are biased for current to flow in a first direction or the current flows in the first direction during a programming operation and biased for a current to flow in a second direction or current is flowing in the second direction during a normal circuit operation, such as a read operation, wherein the first and second directions are opposite of one another. Thus the invention facilitates the use of a low programming potential while minimizing post programming leakage current.
Due to the low programming potential requirement of the invention, memory devices comprising the anti-fuse elements of the invention are successfully programmed using batteries as a power source. Direct consequences of the successful programming using batteries are good post program current-voltage characteristics.
FIG. 1 depicts a circuit of the related art.
FIG. 2 depicts a circuit of the related art.
FIG. 3 three shows the transistor current and drain voltage curves of the circuits of Figures one and two.
FIG. 4 depicts the circuit of the invention.
FIG. 4 depicts the circuit of the invention. An n-channel metal oxide semiconductor (NMOS) transistor 50 and an anti-fuse element S5 are serially connected at serial node 60. The source/drain connection 65 of the transistor 50 has the capability of being electrically connected to a normal operation supply potential Vcc, at normal supply node 70 or connected to a reference potential at reference node 75. Similarly terminal 80 of the anti-fuse device has the capability of being electrically connected to either a programming supply potential, Vpp, at programming supply node 85 or connected to the reference potential at reference node 90. A typical reference potential is ground or zero volts. A typical normal operation supply potential is 5 volts or 3.3 volts, and a typical programming supply potential ranges between 10 and 12 volts. However it is conceivable that the supply potentials at nodes 70 and 85 may have the same value, and it is conceivable that the reference potentials at nodes 75 and 90 may have different values. The switching of source/drain connection 65 and terminal 80 between the supply and reference potentials may be controlled by external programming signals or by internal programming signals. A combination of external and internal signals may control the switching of source/drain connection 65 and terminal 80.
During a programming operation, the dielectric of a selected anti-fuse device is broken down. This breakdown results when the circuit is biased to produce a current flow through the anti-fuse device. The current flow causes the dielectric to weaken which in turn results in an electrical connection between first and second conductive plates of the anti-fuse device. When terminal 80 is connected to the programming supply potential at programming supply node 85, and source/drain connection 65 is connected to the reference potential at reference node 75 a first potential bias is applied across the circuit. The circuit is programmed when the first potential bias is applied. By connecting source/drain connection 65 and terminal 80 in this manner the first potential bias has a polarity which eliminates the transistor source bias during the programming operation, and current can flow in a first direction. If transistor 50 is actuated the dielectric in the antifuse is broken down and current flows in the first direction.
By biasing the circuit with a second potential bias during a normal circuit operation, such as a read operation, with a polarity opposite the polarity of the first potential bias applied during the programming operation leakage current is minimized. The second potential bias is applied to the circuit when terminal 80 is connected to the reference potential at reference node 90 and source/drain connection 65 is connected to the normal operation supply potential at normal supply node 70. By connecting source/drain connection 65 and terminal 80 in this manner the second potential bias has a polarity which can cause current flow or current does flowing a second direction, depending upon the state of the anti-fuse element. That is, if the anti-fuse element has been broken down current can flow through the element in the second direction, and if the anti-fuse element has not been broken down the circuit is biased such that current would flow in the second direction if it were possible. The first and second directions are opposite of one another.
Thus the circuit and method of the invention reverses the polarity of the potential bias applied across the serially connected transistor and anti-fuse device during programming and the polarity of the potential bias applied across the serially connected transistor and anti-fuse device during a normal operation. Thus the invention facilitates the use of a low supply potential to program the device while minimizing leakage current. It is conceivable that in the actual circuit design supply nodes 70 and 85 are the same circuit point, and that reference nodes 75 and 90 are the same circuit point.
Although the circuit and method of the invention have been described in terms of an anti-fuse device the invention has utility in any circuit wherein the direction of the potential bias across the circuit is reversed in order to perform different functions. Modification to the circuitry may also be implemented without detracting from the concept of the invention. Accordingly, the invention should be read as limited only by the claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4943538 *||Mar 10, 1988||Jul 24, 1990||Actel Corporation||Programmable low impedance anti-fuse element|
|US5008855 *||Jul 18, 1989||Apr 16, 1991||Actel Corporation||Method of programming anti-fuse element|
|US5119163 *||Jun 18, 1991||Jun 2, 1992||Sharp Kabushiki Kaisha||Semiconductor device|
|US5148391 *||Feb 14, 1992||Sep 15, 1992||Micron Technology, Inc.||Nonvolatile, zero-power memory cell constructed with capacitor-like antifuses operable at less than power supply voltage|
|US5241496 *||Aug 19, 1991||Aug 31, 1993||Micron Technology, Inc.||Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within a trench shared by a pair of cells|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6249472 *||Dec 18, 1998||Jun 19, 2001||Texas Instruments Incorporated||Semiconductor memory device with antifuse|
|U.S. Classification||365/225.7, 257/50, 365/96, 257/530|
|International Classification||G11C17/16, G11C17/18|
|Cooperative Classification||G11C17/18, G11C17/16|
|European Classification||G11C17/16, G11C17/18|
|Sep 20, 2001||FPAY||Fee payment|
Year of fee payment: 8
|Sep 9, 2005||FPAY||Fee payment|
Year of fee payment: 12