|Publication number||USRE35845 E|
|Application number||US 08/235,022|
|Publication date||Jul 14, 1998|
|Filing date||Apr 28, 1994|
|Priority date||Dec 29, 1989|
|Also published as||DE69031680D1, DE69031680T2, EP0435603A2, EP0435603A3, EP0435603B1, US5109268|
|Publication number||08235022, 235022, US RE35845 E, US RE35845E, US-E-RE35845, USRE35845 E, USRE35845E|
|Original Assignee||Sgs-Thomson Microelectronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (22), Non-Patent Citations (44), Referenced by (3), Classifications (18), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention provides a novel mounting package for RF transistors including a novel thermally conductive electrically insulating mounting pad, and relates to the semiconductor packaging industry.
2. Description of Related Art
The use of semiconductor devices for RF (radio or high frequency) applications has increased dramatically as heat dissipation, size, dependability, and other characteristics have made them particularly suited for many applications. Semiconductor transistors are very small and very difficult to use; therefore, they are generally incorporated into packages. Radio frequency packages are used for holding semiconductor components, particularly transistors, and for providing readily available terminals for connection to other components.
In designing such packages, the tendency of semiconductors to generate heat must be considered. To this end, the semiconductor is frequently mounted on a thermally conductive pad to act as a heat sink and dissipate heat generated by the transistor. However, semiconductors are sensitive to electrical energy, and therefore the thermally conductive pad should also be electrically insulating. Hence, a thermally conducting, electrically insulating material is used for the mounting pad. Commonly, this material is beryllia (beryllium oxide--BeO), although alumina (aluminum oxide--Al2 O3) has occasionally been used.
Beryllia (BeO) has better thermal conductivity than Al2 O3, and is therefore more commonly used. However, care must be taken in handling and processing BeO. BeO is highly toxic. It can be hazardous to the human respiratory system when in powder form. Therefore, care must be exercised if the BeO pad is to be machined or ground. Proper equipment and safeguards are needed to insure that the BeO is handled safely and that improper contact with humans is not made.
Another disadvantage of the prior art packages is that when BeO is used, a "thin" pad of BeO is employed. This pad is attached to the heat sink through the use of a preform. The preform is generally made of gold and tin, or silver and copper. The preform is placed between the mounting pad and the heat sink and the structure is heated. This melts the preform and brazes the pad to the heat sink. This creates two interfaces: pad-to-preform, and preform-to-heat sink. These interfaces decrease the thermal conductivity of the connection. Further, BeO has a high thermal conductivity up to about 200° C. to 250° C., but its performance decrease with increasing temperature.
The BeO pad used is generally about 0.040" to 0.060" thick. Such thickness is required since the mechanical strength of BeO is low. If the pad is not sufficiently thick, the pad may crack or split during attachment, or later upon heating from use.
It has now been discovered that other thermally conductive, electrically insulating materials may be used as mounting pads for mounting transistors and other semiconductors in packages. These materials may be applied directly to the surface of the heat sink in very thin films, or mounted on the heat sink as thin slivers. This increases the thermal conductivity of the package and decreases the overall height of the finished transistor package.
The materials which are useful for the present invention are; boron nitride (BN), diamond, aluminum nitride (AlN), and aluminum oxide/(Al2 O3). The BN, AlN, and Al2 O3 may be deposited by plasma deposition. The diamond thin coating may be deposited by vacuum deposition. Any of the above materials may alternatively be mounted on the heat sink by placing a preform between the heat sink and a sliver of the material and heating the combination to braze the two together. These films or slivers can be substantially thinner than the BeO pads of the prior art, since the materials possess higher mechanical strength. Further, the films are deposited directly on the heat sink, thus eliminating one material-to-material interface.
The FIGURE is a three dimensional expanded view of a package of the present invention.
Referring now to the FIGURE, package 10 of the present invention includes heat sink 20 with capacitor 30. Heat sink 20 is preferably made from tungsten and copper (W+Cu) which have qualities desirable for a heat sink. Heat sink 20 acts as a support for package 10. Capacitor 30 is mounted directly on heat sink 20 and inside of the assembled package 10.
Mounting pad 40 is attached to heat sink 20. Semiconductor 50 is then attached to mounting pad 40. These attachments will be explained further presently. Preform 60 is placed on heat sink 20, around capacitor 30, pad 40 and semiconductor 50. Lamina 70 and 80 are then placed on preform 60. The lamina 70 and 80 act as spacers to allow proper connections to be made to semiconductor 50. Lamina 70 and 80 are co-fired with leads 75 (for connection to semiconductor 50 on the inside) already in place. A second preform 90 is placed on lamina 70 and 80, and lid 100 caps the entire package.
Lamina 70 and 80 are generally made from alumina and allow proper positioning of leads 75 with respect to semiconductor 50. Lid 100 is generally made from kovar, an iron-cobalt alloy. Preforms 60 and 90 are made from gold and tin, or copper and silver. This allows low temperature brazing.
Mounting pad 40 may be made from any of several different materials and may be a sliver of material or a very thin coated layer. Pad 40 may be made of boron nitride, diamond, aluminum nitride, or alumina. Pad 40 is attached to heat sink 20 in different ways depending on the form of the pad.
A pad 40 made from diamond may take two different forms: a single crystal substrate, or a thin film. A single crystal substrate would be from 3 to 4 mils (0.003"-0.004") thick. Such a single crystal substrate would be bonded to heat sink 20 through the use of a gold and tin, or copper and silver preform. The preform is placed between the sliver and heat sink 20. Heat is then applied and the sliver is brazed to the heat sink 20.
The preferred method of using diamond for pad 40 is through vacuum deposition of minute diamond particles onto heat sink 20. This eliminates one material-to-material interface, allowing greater thermal conductivity between the semiconductor and the heat sink, across pad 40. This also reduces the size of pad 40. As previously mentioned, a diamond sliver is usually 3 to 4 mils (0.003"-0.004") thick, but when vacuum deposited, the diamond layer is preferably 10μ (0.00039") and generally between 0.3 and 0.5 mils (0.0003"-0.0005") thick. Whether a diamond sliver or diamond coating is used, the diamond pad 40 is then preliminarily plated with an appropriate metal and then gold plated. Semiconductor 50 is then mounted on the gold plating by applying heat and pressure. The gold plating and silicon semiconductor combine to form a gold-silicon euctectic which holds semiconductor 50 in place.
If pad 40 is made from boron nitride, aluminium nitride or alumina, it may also be applied to heat sink 20 in two different forms: as a thin layer; or as a thin sliver. A sliver of any of these materials would be approximately 8-12 mils (0.008"-0.012") thick. Use of such a sliver would necessitate the use of a preform to braze the sliver (pad 40) to heat sink 20. These materials may also be applied by plasma deposition. . .Such a deposition technique cannot be used with diamond since it involves heating the material until plasma forms. In the case of diamond, it is not likely that the cooling carbon would reform into a diamond lattice structure..!.
Plasma deposition produces a layer of material about 7-8 mils (0.007"-0.008") thick. Plasma deposition requires no preform to secure the coating. Whichever form of boron nitride, aluminium nitride or alumina is used, it must be plated with layers of molybdenum, nickel and gold. Semiconductor 50 is then secured to the gold plating as described above.
Using the techniques described above, the overall thickness of the RF package can be decreased by one-third from about 0.120" to about 0.080". However, if necessary, a Kovar spacer may be included between heat sink 20 and lamina 70 to maintain an overall package thickness of 0.120".
The invention has been described as an RF transistor package and mounting pad in the best mode known to applicant, however, it will be apparent that the invention may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3364400 *||Oct 22, 1964||Jan 16, 1968||Texas Instruments Inc||Microwave transistor package|
|US3489956 *||Apr 27, 1967||Jan 13, 1970||Nippon Electric Co||Semiconductor device container|
|US3500066 *||Jan 10, 1968||Mar 10, 1970||Bell Telephone Labor Inc||Radio frequency power transistor with individual current limiting control for thermally isolated regions|
|US3626259 *||Jul 15, 1970||Dec 7, 1971||Trw Inc||High-frequency semiconductor package|
|US3651434 *||Apr 30, 1969||Mar 21, 1972||Microwave Semiconductor Corp||Microwave package for holding a microwave device, particularly for strip transmission line use, with reduced input-output coupling|
|US3753056 *||Mar 22, 1971||Aug 14, 1973||Texas Instruments Inc||Microwave semiconductor device|
|US3801882 *||Jan 11, 1973||Apr 2, 1974||Us Navy||Thermo-electric mounting method for rf silicon power transistors|
|US3908185 *||Mar 6, 1974||Sep 23, 1975||Rca Corp||High frequency semiconductor device having improved metallized patterns|
|US3936864 *||Oct 4, 1974||Feb 3, 1976||Raytheon Company||Microwave transistor package|
|US3996603 *||Oct 18, 1974||Dec 7, 1976||Motorola, Inc.||RF power semiconductor package and method of manufacture|
|US3999142 *||Nov 12, 1975||Dec 21, 1976||The United States Of America As Represented By The Secretary Of The Army||Variable tuning and feedback on high power microwave transistor carrier amplifier|
|US4161740 *||Nov 7, 1977||Jul 17, 1979||Microwave Semiconductor Corp.||High frequency power transistor having reduced interconnection inductance and thermal resistance|
|US4168507 *||Nov 21, 1977||Sep 18, 1979||Motorola, Inc.||Structure and technique for achieving reduced inductive effect of undesired components of common lead inductance in a semiconductive RF power package|
|US4556899 *||Jun 7, 1982||Dec 3, 1985||Hitachi, Ltd.||Insulated type semiconductor devices|
|US4561010 *||Dec 3, 1982||Dec 24, 1985||Hitachi, Ltd.||Electrically insulating silicon carbide sintered body|
|US4639760 *||Jan 21, 1986||Jan 27, 1987||Motorola, Inc.||High power RF transistor assembly|
|US4649416 *||Jan 3, 1984||Mar 10, 1987||Raytheon Company||Microwave transistor package|
|US4907067 *||May 11, 1988||Mar 6, 1990||Texas Instruments Incorporated||Thermally efficient power device package|
|DE3336867A1 *||Oct 11, 1983||Apr 25, 1985||Licentia Gmbh||Mounting for at least one semiconductor component|
|EP0297569A2 *||Jun 29, 1988||Jan 4, 1989||Sumitomo Electric Industries, Ltd.||Member for semiconductor apparatus|
|GB2084796A *||Title not available|
|JPS6224648A *||Title not available|
|1||"Elimination of Beryllium Oxide (BeO) from DoD Managed or Procured Electrical or Electronics Items", Defense Logistics Agency, Microwave Semiconductor Corp., Dec. 2, 1988.|
|2||Angus, et al. "Low-Pressure, Metastable Growth of Diamond and `Diamondlike` Phases", Science, vol. 241, pp. 913-921, Aug. 19, 1988.|
|3||*||Angus, et al. Low Pressure, Metastable Growth of Diamond and Diamondlike Phases , Science, vol. 241, pp. 913 921, Aug. 19, 1988.|
|4||Anthony et al., "Thermal Diffusivity of Isotopically Enriched 12 C Diamond", Physical Review B, vol. 42, #2, 15 Jul., 1990-I, pp. 1104-1111.|
|5||*||Anthony et al., Thermal Diffusivity of Isotopically Enriched 12 C Diamond , Physical Review B, vol. 42, 2, 15 Jul., 1990 I, pp. 1104 1111.|
|6||Balakov, "Diamond-Like Carbon Coatings: Problems and Achievements", Sov. J. Opt. Technol. 56(6), Jun. 1989, pp. 375-384.|
|7||*||Balakov, Diamond Like Carbon Coatings: Problems and Achievements , Sov. J. Opt. Technol. 56(6), Jun. 1989, pp. 375 384.|
|8||Deshpandey et al., "Plasma Assisted Deposition Techniques and Synthesis of Novel Materials" Thin Solid Films, 163 (1988), pp. 131-147.|
|9||*||Deshpandey et al., Plasma Assisted Deposition Techniques and Synthesis of Novel Materials Thin Solid Films, 163 (1988), pp. 131 147.|
|10||Dyment et al., "Continuous Operation of GaAs Junction Lasers on Diamond Heat Sinks at 200° K.", Applied Physics Letter, vol. 11, #9, 1 Nov. 1967, pp. 292-294.|
|11||*||Dyment et al., Continuous Operation of GaAs Junction Lasers on Diamond Heat Sinks at 200 K. , Applied Physics Letter, vol. 11, 9, 1 Nov. 1967, pp. 292 294.|
|12||*||Elimination of Beryllium Oxide (BeO) from DoD Managed or Procured Electrical or Electronics Items , Defense Logistics Agency, Microwave Semiconductor Corp., Dec. 2, 1988.|
|13||*||Form A 14053, Effective Nov. 1987, The Carborundum Company, Standard Oil Engineered Materials High Thermal Conductivity Ceramics Comparison Product Data Typical Values .|
|14||Form A-14053, Effective Nov. 1987, The Carborundum Company, Standard Oil Engineered Materials-"High Thermal Conductivity Ceramics Comparison Product Data-Typical Values".|
|15||Landstrass et al. "Resistivity of Chemical Vapor Deposited Diamond Films", Appl. Phys. Lett 55(10), 4 Sep. 1989, pp. 975-976.|
|16||*||Landstrass et al. Resistivity of Chemical Vapor Deposited Diamond Films , Appl. Phys. Lett 55(10), 4 Sep. 1989, pp. 975 976.|
|17||Landstrass et al., "Hydrogen Passivation of Electrically Active Defects in Diamond" Appl. Phys. Lett. 55(14), 2 Oct. 1969, pp. 1391-1393.|
|18||*||Landstrass et al., Hydrogen Passivation of Electrically Active Defects in Diamond Appl. Phys. Lett. 55(14), 2 Oct. 1969, pp. 1391 1393.|
|19||*||Lars Peter Andersson, A Review of Recent Work on Hard i C Films , Thin Solid Films, 86 (1981) 193 200.|
|20||Lars-Peter Andersson, "A Review of Recent Work on Hard i-C Films", Thin Solid Films, 86 (1981) 193-200.|
|21||Morelli et al., "Thermal Conductivity of Synthetic Diamond Films", J. Appl. Phys. 64 (6), 15 Sep. 1988 pp. 3063-3066.|
|22||*||Morelli et al., Thermal Conductivity of Synthetic Diamond Films , J. Appl. Phys. 64 (6), 15 Sep. 1988 pp. 3063 3066.|
|23||Nobuo Setaka, "Vapor Deposition of Diamond", Nat'l Institute for Research in Inorganic Materials, Japan, pp. 1156-1163.|
|24||*||Nobuo Setaka, Vapor Deposition of Diamond , Nat l Institute for Research in Inorganic Materials, Japan, pp. 1156 1163.|
|25||*||Patent Abstracts of Japan, vol. 11 No. 198 (E 519)(2645) Jun. 25, 1987 & JP A 62 24648 and JP A 62 24647.|
|26||Patent Abstracts of Japan, vol. 11 No. 198 (E-519)(2645) Jun. 25, 1987 & JP-A-62 24648 and JP-A-62 24647.|
|27||R.C. DeVries, "Synthesis of Diamond Under Metastable Conditions", General Electric Corp. Research & Development, Ann. Rev. Maser. Sci. 1987, 17:161-87.|
|28||*||R.C. DeVries, Synthesis of Diamond Under Metastable Conditions , General Electric Corp. Research & Development, Ann. Rev. Maser. Sci. 1987, 17:161 87.|
|29||R.McPhillips, "Advanced Ceramic Materials from Thermal Conductivity Substrate Applications" Hybrid Circuit Technology, Aug. 1988.|
|30||*||R.McPhillips, Advanced Ceramic Materials from Thermal Conductivity Substrate Applications Hybrid Circuit Technology, Aug. 1988.|
|31||Setaka, "Diamond Synthesis from Vapor Phase and its Growth Process", J. Mater. Res. vol. 4, #3, May/Jun. 1989, pp. 664-670.|
|32||*||Setaka, Diamond Synthesis from Vapor Phase and its Growth Process , J. Mater. Res. vol. 4, 3, May/Jun. 1989, pp. 664 670.|
|33||Spitsyn et al., "Vapor Growth of Diamond on Diamond and Other Surfaces", 1981, 219-226.|
|34||*||Spitsyn et al., Vapor Growth of Diamond on Diamond and Other Surfaces , 1981, 219 226.|
|35||Swan, "The Importance of Providing a Good Heat Sink for Avalanching Transit Time Oscillator Diodes", Proc. IEEE (Letters), vol. 55, p. 451, (1967).|
|36||*||Swan, The Importance of Providing a Good Heat Sink for Avalanching Transit Time Oscillator Diodes , Proc. IEEE (Letters), vol. 55, p. 451, (1967).|
|37||Waltraud Werdecker & Fritz Aldinger, "Aluminum Nitride-An Alternative Ceramic Substrate for High Power Applications in Microcircuits", IEEE 1984, pp. 399-404.|
|38||*||Waltraud Werdecker & Fritz Aldinger, Aluminum Nitride An Alternative Ceramic Substrate for High Power Applications in Microcircuits , IEEE 1984, pp. 399 404.|
|39||Williams et al., "Characterization of Diamond Thin-Films: Diamond Phase Identification, Surface Morphology, and Defect Structures", J. Mater. Res., vol. 4, #2, Mar./Apr. 1989, pp. 373-383.|
|40||Williams et al., "Electron Microscopy of Vapor Phase Deposited Diamond", J. Mater. Res., vol. 5, #4, Apr. 1990, pp. 801-809.|
|41||*||Williams et al., Characterization of Diamond Thin Films: Diamond Phase Identification, Surface Morphology, and Defect Structures , J. Mater. Res., vol. 4, 2, Mar./Apr. 1989, pp. 373 383.|
|42||*||Williams et al., Electron Microscopy of Vapor Phase Deposited Diamond , J. Mater. Res., vol. 5, 4, Apr. 1990, pp. 801 809.|
|43||Zhu et al. "Structural Imperfections in CVD Diamond Films", J. Mater. Res., vol. 4, #3, May/Jun. 1989, pp. 659-663.|
|44||*||Zhu et al. Structural Imperfections in CVD Diamond Films , J. Mater. Res., vol. 4, 3, May/Jun. 1989, pp. 659 663.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6335863 *||Jan 12, 1999||Jan 1, 2002||Sumitomo Electric Industries, Ltd.||Package for semiconductors, and semiconductor module that employs the package|
|US7339791||Jan 18, 2002||Mar 4, 2008||Morgan Advanced Ceramics, Inc.||CVD diamond enhanced microprocessor cooling system|
|US20040183172 *||Oct 7, 2003||Sep 23, 2004||Sumitomo Electric Industries, Ltd.||Package for housing semiconductor chip, and semiconductor device|
|U.S. Classification||257/702, 257/77, 257/707, 257/701|
|International Classification||H01L23/64, H01L23/373, H01L23/66, H01L23/02, H01L23/04|
|Cooperative Classification||H01L23/66, H01L23/642, H01L23/3732, H01L23/3731, H01L2924/0002|
|European Classification||H01L23/64C, H01L23/66, H01L23/373C, H01L23/373D|
|Oct 4, 1999||FPAY||Fee payment|
Year of fee payment: 8
|Oct 7, 2003||FPAY||Fee payment|
Year of fee payment: 12