|Publication number||USRE36097 E|
|Application number||US 08/748,460|
|Publication date||Feb 16, 1999|
|Filing date||Nov 8, 1996|
|Priority date||Nov 14, 1991|
|Also published as||DE4238646A1, DE4238646B4, US5363279, USRE37413|
|Publication number||08748460, 748460, US RE36097 E, US RE36097E, US-E-RE36097, USRE36097 E, USRE36097E|
|Inventors||Gi Bon Cha|
|Original Assignee||Lg Semicon, Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (45), Non-Patent Citations (4), Classifications (55), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly to a semiconductor package suitable for packaging a center pad layout-shaped memory chip wherein paddles of a lead frame are removed and outer leads of a lead frame are not protruded from the package but only exposed to a lower surface of molding resin of a semiconductor package.
2. Description of the Prior Art
Generally, semiconductor packages may be mainly classified into a semiconductor of SOP (small outline package) type and a semiconductor of SOJ (small outline J-lead) type.
In this case, the semiconductor packages are manufactured in accordance to following procedures. A semiconductor chip is attached on paddles of a lead frame and then wire bonding is carried out between inner leads of the lead frame and pads on the semiconductor chip. The wire bonded semiconductor and lead frame are molded by molding resin. Thereafter, the resulting product is subjected to deflash, trimming and forming procedures so that outer leads of the lead frame are protruded from the molded resin and then bent into predetermined shape respectively.
Referring to FIGS. 2 and 3, there are shown a front section and a bottom of a semiconductor package of LOC (lead on chip) type. In the semiconductor package shown in FIGS. 2 and 3, a semiconductor chip 3 is formed with a plurality of bond pads 3a at central portion thereof. Inner leads 4a of a lead frame 4 without paddles are attached on a surface of the semiconductor chip 3 at both sides of the bond pads 3a by means of insulation tapes 6. The inner leads 4a are electrically connected to the bond pads 3a of the semiconductor chip 3 by means of metal wires 7, respectively. Also, power supplying pads of the bond pads 3a are electrically connected to bus bars 5 by metal wires 7, respectively. Thereafter, the resulting semiconductor chip 3 and the inner leads 4a of the lead frame 4 are molded by molding resin 1.
The above-mentioned prior semiconductor packages are manufactured in such a manner that a semiconductor chip aggregate is subjected to a sawing step for dividing the semiconductor chip aggregate into separate semiconductor chips 3 and the semiconductor chip 3 is subjected to a die bonding step for attaching the separated semiconductor chip 3 to a lead frame 4, a wire bonding step for electrically connecting bond pads 3a of the semiconductor chip 3 to inner leads 4a of the lead frame 4 respectively, a molding step for enveloping the wire bonded semiconductor chip 3 and lead frame 4, a deflashing step, a solder plating step, a trimming step for cutting dampers of the lead frame 4, a forming step for bending outer leads into a certain shape, and a marking step.
The semiconductor package prepared as described above have outer leads protruded from the mold resin. The outer leads are formed into a certain shape and then mounted on a printed circuit board.
However, the prior semiconductor packages have various disadvantages as follows. The prior semiconductor packages occupy large space due to the outer leads protruded from mold resins when the semiconductor packages are mounted on printed circuit boards.
Since the semiconductor packages have outer mechanical shock when their forming procedure, fine gaps may occur in contact areas between outer leads protruded from package bodies and mold resins, thereby causing humidity resistant property to be deteriorated due to the gaps.
Also, since the semiconductor packages require a trimming step and a forming step after a molding procedure, manufacturing process of the packages becomes complicated so that their manufacturing cost and poor products occurring rate are increased.
In addition, in case of the LOC type of semiconductor packages using lead frames without paddles, electrical property is decreased because of their long length between inner leads and outer leads.
Furthermore, so-called "good rate" which is a rate of good products in products identified as poor packages is increased because of poor lead contacts in testing of finished products.
Therefore, the present invention is made in view of the above-described prior art problems and an object of the invention is to provide a semiconductor package which is designed to occupy small space required to be mounted on a printed circuit board and to reduce manufacturing cost by omitting manufacturing procedures next to a molding procedure.
Another object of the invention is to provide a semiconductor package which has improved lead conductance and thus electrical property by reducing length between its inner leads and outer leads.
In accordance with the present invention, these object can be accomplished by providing a semiconductor package comprising: a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface; a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads; insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads; metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively; and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside.
Since the leads of the invention are shortened in length between their inner leads wire-bonded to the bond pads of the semiconductor chip and their outer leads exposed to outside, it is possible to improve lead conductance in a LOC type of semiconductor package and to radiate easily heat occurring in operation of the chip due to their short leads. Particularly, the semiconductor package is appropriate to package a semiconductor chip of 16-mega-bit DRAM or greater which is formed with bond pads at its central portion.
The leads are bent into a certain shape respectively at their inner leads and the outer leads and then the outer leads are attached to polyimide based adhesive tapes. The inner leads of the leads are attached to a bottom surface of the semiconductor chip via insulating films or insulating paste applied to the bottom surface. The attached lead frame and the semiconductor chip are molded such that the outer leads are not protruded from the molded resin but exposed to outside.
In accordance to the invention as described above, paddles are omitted and the outer leads are not protruded from the package but exposed to outside so that the exposed outer leads can be connected to a connection pattern of a printed circuit board. Since the semiconductor package has not protruded outer leads, space occupied by the package is reduced when the package is mounted on a printed circuit board. Also, it is possible to abbreviate trimming and forming procedures next to a molding procedure in its manufacturing process.
These and other objects and aspects of the invention will become apparent from the following description of an embodiment with reference to the accompanying drawings in which:
FIG. 1A is a schematic view of a prior SOP type of semiconductor package;
FIG. 1B is a schematic view of a prior SOJ type of semiconductor package;
FIG. 2 is a vertical sectional view of a prior LOC type of semiconductor package;
FIG. 3 is a bottom plan view of the semiconductor package shown in FIG. 2, showing its inner construction;
FIG. 4 is a vertical sectional view of a semiconductor package according to the present invention;
FIG. 5 is a bottom plan view of the semiconductor package shown in FIG. 4, showing its inner construction;
FIG. 6A is a front elevational view of a semiconductor package according to the invention; and
FIG. 6B is a bottom plan view of the semiconductor package shown in FIG. 6A.
The present invention will now be described by referring to FIGS. 4 to 6 in the accompanying drawings. FIG. 4 shows a vertical section of a semiconductor package according to the present invention and FIG. 5 shows an inner construction of the semiconductor package shown in FIG. 4.
As shown in the drawings, the semiconductor package of the present invention comprises a semiconductor chid 3 which is formed with a plurality of bond pads 3a at a central portion of its bottom surface, a lead frame 10 including leads 11 connected to bond pads for input/output of the bond pads 3a respectively and bus bars 12 connected to power supplying pads of the bond pads 3a, insulation adhesives 6 for attaching inner leads 11 of the leads 11 and inner leads 12a of the bus bars 12 to a bottom surface of the semiconductor chip 3 formed with the bond pads 3a, metal wires 7 for electrically connecting the inner leads 11a of the leads 11 and the inner leads 12a of the bus bars 12 to the bond pads 3a respectively, and a molding compound 8 enveloping the semiconductor chip assembly with outer leads 11b and 12b of the lead frame 10 exposed to outside.
In this description, the substantially identical or similar elements of the semiconductor package of the invention to those of the prior art illustrated in FIGS. 1 to 3 are designated by the similar reference characters.
The plurality of inner leads 11a, 12a and outer leads 11b, 12b of the leads 11 and the bus bars 12 are bent into a predetermined shape respectively and arranged in a row. Then, the outer leads 11b, 12b are attached to adhesive tapes (not shown) at their outer surfaces so that the leads 11 and the bus bars 12 are integrally held. The adhesive tapes.Iadd., which may serve as a support during a molding procedure, .Iaddend.are removed after . .a.!. .Iadd.the .Iaddend.molding procedure.
The lead frame 10 is attached to the semiconductor package 3 in such a manner that insulating adhesives 6 such as insulating films and insulating paste are applied to the bottom surface of the semiconductor chip 3 formed with the bond pads 3a and then the inner leads 11a, 12a of the leads 11 and the bus bars 12 are attached to the insulating adhesives 6.
Also, the leads 11 and the bus bars 12 of the semiconductor package of the present invention are shorter than those of a prior LOC type of semiconductor package in lengths between its inner leads 11a, 12a and its outer leads 11b, 12b so that lead conductance is increased when a memory chip of 16-mega-bit DRAM or greater is packaged. In addition, heat occurring in operation of chip can be easily discharged from the short leads.
FIG. 6A shows a front side of the semiconductor package of the invention and FIG. 6B shows a bottom surface of semiconductor package of the invention. As shown in FIG. 6A, the outer leads 11b and 12b of the leads 11 and the bus bars 12 are not protruded from the semiconductor package but are flush with the bottom surface of the semiconductor package.
That is, the outer leads 11b and 12b of the leads 11 and the bus bars 12 are arranged in a row at the bottom surface of the package and faces to outside to be contacted with elements of a printed circuit board, as shown in FIG. 6B. .Iadd.As shown in FIGS. 4 and 6B, the leads may be elongated and contoured and extend away from the bottom surface, and the exposed portion of the leads may occupy less than a majority portion of the bottom surface..Iaddend.
A manufacturing process of the semiconductor package as constructed above will be described in detail hereinafter.
First, a semiconductor chip 3 which has been cut separately is applied with insulating adhesive 6 such insulating film and insulating paste at its bottom surface formed with bond pads 3a. Inner leads 11a and 12a of leads 11 and bus bars 12 are attached to the bottom surface of the chid via the insulating adhesive 6 applied to the bottom surface.
Thereafter, the lead frame 10 attached to the semiconductor chip 3 is die-attached in a wire bonder (a wire bonding apparatus) and subjected to a wire bonding procedure for electrically connecting the inner leads 11a, 12a of the leads 11 and the bus bars 12 to the bond pads 3a by metal wires 7 such as gold and aluminum wires.
Subsequently, the resulting semiconductor chip assembly is subjected to a known transfer molding procedure to be enveloped. Then, as adhesive tapes attached to a bottom surface of the molded resin are removed, the outer leads 11b and 12b of the leads 11 and the bus bars 12 are exposed to outside. Thereafter, as the bottom surface of the molded package and the exposed outer leads are simply removed by a deflash procedure, the manufacturing process of the semiconductor package is completed.
The semiconductor package of the invention as prepared above is mounted on a printed circuit board such that the exposed outer leads 11b and 12b are connected to a pattern of printed circuit board by a soldering.
As apparent from the above description, the present invention can leave out procedures next to a molding step. That is, since a prior semiconductor package has outer leads protruded therefrom, a manufacturing process of a prior semiconductor package requires a forming procedure for bending the protruded outer leads and a trimming procedure for cutting dampers of leads. However, since leads according to the invention are attached to adhesive tapes to form an integral lead frame and outer leads of leads are exposed to outside, a manufacturing process of the invention does not require trimming and forming procedures.
Therefore, the present invention has advantages in that since the number of manufacturing steps is significantly reduced, occurrence of poor products and manufacturing cost are reduced.
Also, since the semiconductor package of the invention has not outer leads protruded therefrom; space occupied by the semiconductor package is reduced thereby allowing the packages to be densely mounted when the packages are mounted on a printed circuit board.
In addition, since the semiconductor package of the invention has leads shortened as possible as, it is possible to improve its electrical property and to radiate heat easily as compared with prior art.
While prior semiconductor package may have gaps between outer leads and a molded resin due to outer shock applied to the outer leads during trimming and forming procedures, the semiconductor package of the invention has outer leads exposed to out side and does not require trimming and forming procedures so that the outer leads are not shocked. Therefore, the semiconductor package of the invention can prevent gaps from occurring in the contact area and thus improve humidity resistance. Also, since the semiconductor package is tested in state of tip, the test can be precisely carried out without a particular testing socket. That is, "Good rate" can be reduced.
Changes in construction will occur to those skilled in the art and various apparently different modifications and embodiments may be made without departing from the scope of the invention. The matter set forth in the foregoing description and accompanying drawings is offered by way of illustration only. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3940786 *||Feb 4, 1975||Feb 24, 1976||Amp Incorporated||Device for connecting leadless integrated circuit package to a printed circuit board|
|US4532419 *||Sep 1, 1983||Jul 30, 1985||Sony Corporation||Memory card having static electricity protection|
|US4539472 *||Jan 6, 1984||Sep 3, 1985||Horizon Technology, Inc.||Data processing card system and method of forming same|
|US4937656 *||Nov 21, 1988||Jun 26, 1990||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device|
|US5107325 *||Apr 11, 1990||Apr 21, 1992||Seiko Epson Corporation||Structure and method of packaging a semiconductor device|
|US5122860 *||Aug 25, 1988||Jun 16, 1992||Matsushita Electric Industrial Co., Ltd.||Integrated circuit device and manufacturing method thereof|
|US5157480 *||Feb 6, 1991||Oct 20, 1992||Motorola, Inc.||Semiconductor device having dual electrical contact sites|
|US5166866 *||May 29, 1991||Nov 24, 1992||Samsung Electronics Co., Ltd.||Semiconductor package|
|US5172214 *||Apr 10, 1992||Dec 15, 1992||Motorola, Inc.||Leadless semiconductor device and method for making the same|
|US5229846 *||Aug 12, 1991||Jul 20, 1993||Kabushiki Kaisha Toshiba||Semiconductor device having noise reducing die pads|
|US5235207 *||Dec 2, 1992||Aug 10, 1993||Hitachi, Ltd.||Semiconductor device|
|US5436500 *||Dec 21, 1992||Jul 25, 1995||Samsung Electronics Co., Ltd.||Surface mount semiconductor package|
|US5583375 *||Dec 14, 1992||Dec 10, 1996||Hitachi, Ltd.||Semiconductor device with lead structure within the planar area of the device|
|US5693573 *||Jan 17, 1997||Dec 2, 1997||Lg Semicon Co., Ltd.||Semiconductor package lead deflash method|
|DE3911711A1 *||Apr 10, 1989||Oct 11, 1990||Ibm||Modul-aufbau mit integriertem halbleiterchip und chiptraeger|
|EP0198194A1 *||Mar 4, 1986||Oct 22, 1986||International Business Machines Corporation||Packaged semiconductor chip|
|EP0465143A2 *||Jun 28, 1991||Jan 8, 1992||AT&T Corp.||Molded hybrid IC package and lead frame therefore|
|EP0501830A2 *||Feb 28, 1992||Sep 2, 1992||Texas Instruments Incorporated||Insulated lead frame for semiconductor packaged devices|
|JPH0247061A *||Title not available|
|JPH0263142A *||Title not available|
|JPH02246125A *||Title not available|
|JPH02298146A *||Title not available|
|JPH03131059A *||Title not available|
|JPH03151058A *||Title not available|
|JPH05166964A *||Title not available|
|JPH06132453A *||Title not available|
|JPH06236956A *||Title not available|
|JPS622560A *||Title not available|
|JPS5116701A *||Title not available|
|JPS5811198A *||Title not available|
|JPS6015786A *||Title not available|
|JPS6068488A *||Title not available|
|JPS6276540A *||Title not available|
|JPS6367763A *||Title not available|
|JPS57176751A *||Title not available|
|JPS60183745A *||Title not available|
|JPS60257159A *||Title not available|
|JPS61222715A *||Title not available|
|JPS62134944A *||Title not available|
|JPS62154769A *||Title not available|
|JPS62249464A *||Title not available|
|JPS62298146A *||Title not available|
|JPS63151058A *||Title not available|
|JPS63258050A *||Title not available|
|JPS63296252A *||Title not available|
|1||Bregmann, Mark F. and Kovac, Carolin A; "Plastic for VLSI-Based Computers"; Jun. 1968, H.6, S.75-80; In: Solid State Technology.|
|2||*||Bregmann, Mark F. and Kovac, Carolin A; Plastic for VLSI Based Computers ; Jun. 1968, H.6, S.75 80; In: Solid State Technology.|
|3||Goodenough, Frank: "Mixing Gold and Aluminum Bond Wires on Power Ics Cuts Cost and Ups Reliability"; 1990; p. 34; In: Electronic Design, 11, H..19.|
|4||*||Goodenough, Frank: Mixing Gold and Aluminum Bond Wires on Power Ics Cuts Cost and Ups Reliability ; 1990; p. 34; In: Electronic Design, 11, H..19.|
|U.S. Classification||361/773, 257/693, 257/691, 361/783, 438/124, 174/533, 361/775, 438/123, 361/813|
|International Classification||H01L23/28, H01L23/12, H01L23/495, H01L23/50, H01L23/31|
|Cooperative Classification||H01L2924/00014, H01L2924/181, H01L2224/451, Y10T29/49146, Y10T29/49172, Y10T29/49121, H01L2924/07802, H01L24/48, H01L24/49, H01L2224/73215, H01L2224/32245, H01L2224/49109, H01L2924/01082, H01L23/4951, H01L2924/01013, H01L23/50, H01L2224/04042, H01L2924/01023, H01L2924/01033, H01L2224/45124, H01L2924/01004, H01L2924/01079, H01L2224/48247, H01L2224/48091, H01L2224/85399, H01L2924/01078, H01L2224/45144, H01L2224/06136, H01L24/06, H01L23/3107, H01L24/45, H01L2224/4826, H01L2224/05599, H01L2924/014, H01L2224/49171, H01L2224/48599, H01L2224/48699|
|European Classification||H01L24/06, H01L23/31H, H01L23/50, H01L23/495A4|
|Apr 11, 2002||FPAY||Fee payment|
Year of fee payment: 8
|Apr 14, 2006||FPAY||Fee payment|
Year of fee payment: 12