|Publication number||USRE36311 E|
|Application number||US 08/253,151|
|Publication date||Sep 21, 1999|
|Filing date||Jun 2, 1994|
|Priority date||Dec 22, 1987|
|Also published as||DE3855603D1, DE3855603T2, EP0322041A2, EP0322041A3, EP0322041B1, US5065213, US5118635|
|Publication number||08253151, 253151, US RE36311 E, US RE36311E, US-E-RE36311, USRE36311 E, USRE36311E|
|Inventors||Ferruccio Frisina, Giuseppe Ferla|
|Original Assignee||Sgs-Thomson Microelectronics, S.R.L.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (34), Non-Patent Citations (2), Referenced by (2), Classifications (12), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a divisional of co-pending application Ser. No. 07/288,405 filed on Dec. 21, 1988, now U.S. Pat. No. 5,065,213.
This invention relates to an integrated high-voltage bipolar power transistor and low-voltage MOS power transistor structure in an emitter switching configuration and to a manufacturing process therefore.
Emitter switching is a circuit configuration in which a low-voltage power transistor (typically an MOS transistor) cuts off the emitter current of a high-voltage power transistor (typically a bipolar transistor) in order to switch it off. This configuration, which up until now was obtained by means of discrete components, offers the following advantages:
it increases the strength of bipolar transistor as far as the possibility of inverted secondary ruptures (ESB) occurring are concerned;
it combines the current and voltage carrying capacity of a piloted transistor and the high speed of a low-voltage transistor;
it enables the system to be piloted directly with linear logic circuits, through the MOS gate.
In view of the advantages that an integrated circuit generally offers, as compared to an analog circuit obtained by means of discrete components, the object of this invention is to provide a high-voltage bipolar power transistor and a low-voltage MOS power transistor, connected together in the emitter switching configuration, and integrated in a single chip of semiconductor material.
The integrated high-voltage bipolar power transistor and vertical low-voltage MOS power transistor structure, in the emitter switching configuration of the invention comprises:
an N+ type semiconductor substrate,
an overlying semiconductor layer,
a first P type region buried in the aforesaid layer,
a second P type region connecting the first aforesaid region on the surface, the first and second region constituting the base region of the bipolar transistor, and
a third N+ type region adjoining the aforesaid first region from below and constituting the emitter region of the bipolar transistor.
According to the invention, the semiconductor layer consists of a first N-type epitaxial layer and a second N-type epitaxial layer grown on it, the first region is located in the first epitaxial layer, in the vicintity of the surface adjacent to the second epitaxial layer, and the second region is located in the second epitaxial layer. The third region can consist of a completely buried layer located astride between the boundary of the first and second epitaxial layer, the body and source regions of the MOS can be located in the second epitaxial layer, in the vicinity of its surface and above the third region. The drain region of the MOS consists substantially of the region between the third region and the aforesaid body regions. Alternatively an integrated high-voltage bipolar power transistor and horizontal low-voltage MOS power transistor structure, in the emitter switching configuration comprises:
an N+ type semiconductor substrate,
an N- type epitaxial layer grown on the substrate,
a first P+ type region, constituting the base of the bipolar transistor, located in the layer in the vicinity of its surface, and
a second N+ type region, constituting the emitter of the bipolar transistor, adjoining the aforesaid first region from below and from the side and adjoining the surface of the layer from above. According to the invention in the N- type epitaxial layer and in the vicinity of its surface there is a third P+ conductivity region as well as a fourth and a fifth N+ type region. These latter regions constutute the MOS source and gate regions respectively and being adjacent from below and from the side to the aforesaid third region. The metal coatings of the MOS transistor drain and of the bipolar transistor emitter are interconnected by means of tracks of conductor material.
A process for manufacturing an integrated high-voltage bipolar power transistor and vertical low-voltage MOS power transistor structure, in the emitter switching configuration is characterized by the fact that:
a second N conductivity epitaxial layer, designed to constitute the drain region of the MOS transistor and at the same time automatically form the connection between the drain of the MOS transistor and the emitter of the bipolar transistor, is grown on the first epitaxial layer,
the body, the source and the gate of the MOS transistor are then created in the second epitaxial layer, by means of the known processes, in correspondence with the aforesaid buried emitter zone of the bipolar transistor, and
a P+ type region, which enables the base region of the bipolar transistor to be electrically connected on the surface, is also created at the side of said MOS transistor, by means of the known techniques of oxidation, photomasking, implantation and diffusion.
Alternatively, the process is characterized in that:
a second P+ type region, separated from the first by a region of the epitaxial layer, is created in the epitaxial layer simultaneously to said first region,
a fourth and a fifth N+ type region, designed to constitute the MOS source and drain region respectively, are created within the second region, and
the deposition of tracks of conductor material designed to electrically interconnect the emitter and drain metal coatings is carried out simultaneously to the deposition of the films of conductor material designed to form the gate terminals and the metal coating which ensure the ohmic contact with the MOS source and drain regions and with the base and emitter regions of the bipolar transistor.
The above and other objects, features and advantages of our invention will become more readily apparent from the following description, reference being made to the accompanying highly diagrammatic drawing in which:
FIG. 1 is a circuit diagram which shows the equivalent electrical circuit of the 4-terminals integrated structures, which the invention intends to realize;
FIGS. 2-7 are diagrammatic sections which show a structure according to the invention, in the vertical MOS power transistor version, during the various stages of the manufacturing process;
FIG. 8 is a section which shows the structure obtained at the end of the process referred to in the previous FIGS. 2-7;
FIG. 9 is a diagram of the concentrations of the various types of doping agent along a section of the structure of FIG. 7;
FIGS. 10-11 are sections which show a structure according to the invention, in the horizontal MOS power transistor version, during the various stages of the manfacturing process; and
FIG. 12 is a section which shows a schematic representation of the structure obtained at the end of the process referred to in FIGS. 10-11.
FIG. 1 shows the equivalent electrical circuit of the 4-terminal integrated structures that the invention intends to provide.
This circuit consists of a high-voltage bipolar power transistor T connected by means of its emitter to the drain of a low-voltage MOS power transistor P.
The various stages of the manufacturing process of the integrated structure, in the vertical MOS version, are described hereunder.
A first high resistivity N- conductivity epitaxial layer 2 is grown on an N+ type substrate 1 (FIG. 2). A P+ type region 3 is then obtained, by deposition or implantation and subsequent diffusion, on said layer 2 (FIG. 3). An N+ type region 4 is then obtained by means of the same process (FIG. 4). This is followed by the growth of a second N type epitaxial layer 5 (FIG. 5) and, by the known procedures of oxidation, photomasking, implantation and diffusion, the creation of the P+ type regions 8, which enable the region 3 constituting the base of the bipolar transistor to be connected on the surface (FIG. 6). A low-voltage vertical MOS power transistor and in particular the relative P conductivity body regions 6, N+ type source regions 7 (FIG. 7), the gate 9 and the metal coatings 10, 11 and 14 for ensuring the ohmic contact with the regions 6, 7, 8 and the substrate 1 (FIG. 8) are then created in the area between the two regions 8, according to known procedures.
FIG. 8 shows the final structure, as it appears after addition of the terminals C (collector). B (base), S (source) and G (gate) and the insulating layer 12 of the gate 9 (said gate being connected to the relative terminal by means of the insulated conductor 13). Regions 1, 2, 3 and 4 of the figure constitute, respectively, the collector, the base and the emitter of a bipolar transistor, while region 5 constitutes the drain of the MOS. Said drain is consequently connected directly to the emitter of the bipolar transistor thus forming a structure having as its equivalent circuit the circuit of FIG. 1.
The emitter 4 represents a completely buried N+ type active region; by growing a second N type epitaxial layer 5 it is thus possible to connect the drain of the MOS to the emitter 4 of the bipolar transistor,
The profile of the concentration (Co) of the various types of doping agent in the different regions of the structure, along section A--A of FIG. 7, is shown in FIG. 9, where axis x refers to the distance from the upper surface of the structure.
The manufacturing process of the integrated structure, in the horizontal MOS power transistor version, includes the following stages.
A high resistivity N- type epitaxial layer 22, which is designed to constitute the collector of the bipolar transistor, is grown on a N+ type substrate 21 (FIG. 10). Two P+ type regions 23 and 24 are then created simultaneously on said layer, by the known processes of deposition or implantation and subsequent diffusion, the first of which being destined to act as a base for the bipolar transistor and the second to receive the MOS.
By means of the known processes of oxidation, photomasking, deposition or implantation and subsequent diffusion, an N+ type region 25 which is destined to act as the emitter of the bipolar transistor is created within the region 23, while two N+ type regions 26 and 27 which are destined to act as the source and the drain of the MOS are created within the region 24 (FIG. 11). This is followed by the formation of the MOS gate 28, the gate insulating layer 29, the metal coatings 30, 31, 32, 33 and 34, which are designed to ensure the ohmic contact with the underlying regions, and lastly the connections to the terminals S, G, B and C (FIG. 12).
The aforesaid metal coatings also include the formation of a track 35 for connecting the drain D to the emitter E, so as to achieve the connection of the two transistors in the configuration of FIG. 1.
In both the vertical MOS and horizontal versions, the final structure obtained is provided with 4 terminals, 3 of said terminals being located on one face of the chip and the 4th on the other face.
The described process can obviously be used to simultaneously obtain, on the same chip, several pairs of bipolar and MOS transistors having a collector terminal in common and their base contacts, sources and gates connected to three respective common terminals by means of a metal coating carried out on the front of the chip at the end of the process.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3544863 *||Oct 29, 1968||Dec 1, 1970||Motorola Inc||Monolithic integrated circuit substructure with epitaxial decoupling capacitance|
|US3580745 *||May 27, 1966||May 25, 1971||Philips Corp||Semiconductor device|
|US3880676 *||Oct 29, 1973||Apr 29, 1975||Rca Corp||Method of making a semiconductor device|
|US4032956 *||Apr 17, 1975||Jun 28, 1977||Sony Corporation||Transistor circuit|
|US4120707 *||Mar 30, 1977||Oct 17, 1978||Harris Corporation||Process of fabricating junction isolated IGFET and bipolar transistor integrated circuit by diffusion|
|US4151006 *||Apr 19, 1977||Apr 24, 1979||U.S. Philips Corporation||Method of manufacturing a semiconductor device|
|US4210925 *||Feb 7, 1978||Jul 1, 1980||Harris Corporation||I2 L Integrated circuit and process of fabrication|
|US4239558 *||May 30, 1979||Dec 16, 1980||Mitsubishi Denki Kabushiki Kaisha||Method of manufacturing semiconductor devices utilizing epitaxial deposition and triple diffusion|
|US4277794 *||Sep 6, 1979||Jul 7, 1981||Thomson-Csf||Structure for logic circuits|
|US4311532 *||Jul 27, 1979||Jan 19, 1982||Harris Corporation||Method of making junction isolated bipolar device in unisolated IGFET IC|
|US4315781 *||Apr 23, 1980||Feb 16, 1982||Hughes Aircraft Company||Method of controlling MOSFET threshold voltage with self-aligned channel stop|
|US4344081 *||Apr 14, 1980||Aug 10, 1982||Supertex, Inc.||Combined DMOS and a vertical bipolar transistor device and fabrication method therefor|
|US4425516 *||May 1, 1981||Jan 10, 1984||Zytrex Corporation||Buffer circuit and integrated semiconductor circuit structure formed of bipolar and CMOS transistor elements|
|US4458408 *||Apr 11, 1983||Jul 10, 1984||Motorola, Inc.||Method for making a light-activated line-operable zero-crossing switch|
|US4483738 *||Feb 3, 1984||Nov 20, 1984||Itt Industries, Inc.||Method for manufacturing bipolar planar transistors|
|US4523215 *||Jan 21, 1981||Jun 11, 1985||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device|
|US4667393 *||Aug 21, 1985||May 26, 1987||Sgs Microelettronica S.P.A.||Method for the manufacture of semiconductor devices with planar junctions having a variable charge concentration and a very high breakdown voltage|
|US4721684 *||Dec 20, 1985||Jan 26, 1988||Sgs Microelettronica Spa||Method for forming a buried layer and a collector region in a monolithic semiconductor device|
|US4780430 *||Sep 28, 1987||Oct 25, 1988||Sgs Microelettronica S.P.A||Process for the formation of a monolithic high voltage semiconductor device|
|US4814288 *||Jul 10, 1987||Mar 21, 1989||Hitachi, Ltd.||Method of fabricating semiconductor devices which include vertical elements and control elements|
|US4879584 *||Feb 10, 1988||Nov 7, 1989||Kabushiki Kaisha Toshiba||Semiconductor device with isolation between MOSFET and control circuit|
|US4881119 *||Feb 2, 1989||Nov 14, 1989||U.S. Philips Corp.||Semiconductor devices|
|US4892836 *||Mar 23, 1987||Jan 9, 1990||Sgs Microelettronica S.P.A.||Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices|
|US4898836 *||Apr 21, 1989||Feb 6, 1990||Sgs-Thomson Microelectronics S.R.L.||Process for forming an integrated circuit on an N type substrate comprising PNP and NPN transistors placed vertically and insulated one from another|
|US4935799 *||Dec 13, 1988||Jun 19, 1990||Mutsuhiro Mori||Composite semiconductor device|
|US4947231 *||Oct 18, 1988||Aug 7, 1990||Sgs-Thomson Microelectronics S.R.L.||Integrated structure with active and passive components enclosed in insulating pockets and operating at higher than the breakdown voltage between each component and the pocket containing it|
|US4969030 *||Apr 3, 1990||Nov 6, 1990||Sgs-Thomson Microelectronics S.P.A.||Integrated structure for a signal transfer network, in particular for a pilot circuit for MOS power transistors|
|US5065213 *||Dec 21, 1988||Nov 12, 1991||Sgs-Thomson Microelectronics S.R.L.||Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process|
|US5118635 *||Aug 23, 1991||Jun 2, 1992||Sgs-Thomson Microelectronics S.R||Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process|
|US5119161 *||Jun 14, 1990||Jun 2, 1992||Sgs-Thomson Microelectronics S.R.L.||Semiconductor device comprising a control circuit and a power stage with a vertical current flow, integrated in monolithic form on a single chip|
|UST892019 *||Jan 27, 1969||Nov 30, 1971||Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance|
|EP0322040A2 *||Dec 16, 1988||Jun 28, 1989||SGS-THOMSON MICROELECTRONICS S.r.l.||Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip|
|EP0322041A2 *||Dec 16, 1988||Jun 28, 1989||SGS-THOMSON MICROELECTRONICS S.r.l.||Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process|
|EP0347550A2 *||Apr 21, 1989||Dec 27, 1989||Texas Instruments Incorporated||Process for fabricating isolated vertical and super beta bipolar transistors|
|1||Blanchard, "A Power Transistor With an Integrated Thermal Feedback Mechanism," Master of Science Dissertation (1970).|
|2||*||Blanchard, A Power Transistor With an Integrated Thermal Feedback Mechanism, Master of Science Dissertation (1970).|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6395593 *||Apr 17, 2000||May 28, 2002||Texas Instruments Incorporated||Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration|
|US6759730 *||Sep 18, 2001||Jul 6, 2004||Agere Systems Inc.||Bipolar junction transistor compatible with vertical replacement gate transistor|
|U.S. Classification||438/133, 438/138|
|International Classification||H01L21/331, H01L29/73, H01L29/78, H01L29/739, H01L27/06, H01L21/8249, H01L27/07|
|Cooperative Classification||Y10S148/009, H01L27/0716|
|Nov 22, 1999||FPAY||Fee payment|
Year of fee payment: 8
|Nov 4, 2003||FPAY||Fee payment|
Year of fee payment: 12