|Publication number||USRE36472 E|
|Application number||US 08/405,435|
|Publication date||Dec 28, 1999|
|Filing date||Mar 16, 1995|
|Priority date||Mar 22, 1989|
|Publication number||08405435, 405435, US RE36472 E, US RE36472E, US-E-RE36472, USRE36472 E, USRE36472E|
|Inventors||Sandro Storti, Bruno Murari, Franco Consiglieri|
|Original Assignee||Stmicroelectronics, S.R.L.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (10), Classifications (10), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
.Iadd.This application is a continuation of Ser. No. 08/010,282, now abandoned, which is an application for reissue of U.S. Pat. No. 4,989,114..Iaddend.
1. Field of the invention
The present invention relates to an integrated circuit employing NPN power transistors for DC driving an external load, particularly an electric motor, and having a protection against an accidental inversion of polarity of the supply.
2. Description of the prior art
Full-bridge or half-bridge output driving stages, monolithically integrated by employing a junction isolation technique for bidirectional DC driving of motors by means of integrated power switches, are known and widely used. In these integrated power stages the N-type transistors (bipolar NPN or N-channel MOS transistors) are much more efficient than P-type transistors. In practice bridge or half-bridge circuits for high level currents may be economically implemented in an integrated form only if the power switching transistors are of the N-type.
A typical integrated bridge circuit of this kind is shown in FIG. 1. The positive pole of the supply is switched, respectively by the two (high side) NPN power transistors TN1 and TN2, on two output terminals 1 and 2, across which the motor M to be driven is connected. The bridge circuit is completed by two (low side) power transistors TN3 and TN4 which are driven so as to connect to the negative supply pole (ground) the output terminals 1 and 2, respectively. It is also a common practice to drive the two high side switches TN1 and TN2 by means of the two drive PNP transistors TP5 and TP6, respectively, to the base of which the respective drive signals are fed.
The presence of a parasitic diode (respectively D1 and D2 in the circuit diagram of FIG. 1) between an N-type collector C and the P-type substrate S connected to ground of the integrated circuit is intrinsic to such an integrated structure employing a junction-type isolation of an NPN transistor depicted in FIG. 3. In the perspective sectional view of the integrated structure of an NPN transistor of FIG. 3, the presence of this parasitic diode D1 (D2) is schematically shown by means of the relative graphic symbol. The hatched portions of the cross section identify P-type regions while the non-hatched portions identify N-type regions.
Should the supply polarity be accidentally inverted, these parasitic diodes D1 and D2 of the integrated NPN transistors TN1 and TN2 become directly biased and the current passing through these diodes may reach destructive levels.
In order to overcome this problem it is known in the art to use a circuit, such as the one depicted in FIG. 2, wherein a polarity guard diode D3 is employed, which when the supply is accidentally applied with an inverted polarity remains reverse biased thus preventing current flow.
This known solution is not free of drawbacks. In fact, by observing the circuit of FIG. 1, it is easily recognizable that the total voltage drop of the load driving bridge circuit is given by the following expression (for a first diagonal of the bridge):
VCESAT (TP5)+VBE(TN1)+VCESAT (TN4)
or (for the other diagonal of the bridge):
VCESAT (TP6)+VBE(TN2)+VCESAT (TN3)
while in the case of the circuit provided with the guard diode of FIG. 2, the total voltage drop of the circuit is similarly given by the expression (for a first diagonal):
VF (D3)+VCESAT (TP5)+VBE(TN1)+VCESAT (TN4)
or (for the other diagonal):
VF (D3)+VCESAT (TP6)+VBE(TN2)+VCESAT (TN3).
It is evident that the use of a diode D3 for protection against polarity inversion of the supply penalizes the electrical efficiency of the circuit by introducing an additional voltage drop VF (D3) which, in a normal operating condition may be comprised between about 600 mV and 1.2 V.
Through the present invention it is possible to reduce down to almost nullifying the additional voltage drop across a guard diode for protection against polarity inversion of the supply though preserving fully the protection afforded by the polarity guard diode.
This objective is fulfilled by connecting in common the emitters of two PNP transistors used to drive the two high-side output power switches (NPN transistors) and directly to the power supply rail.
The characteristics and advantages of the circuit of the present invention will become evident through the following detailed description of preferred embodiments depicted for purely illustrative and nonlimitative purposes in the attached drawings, wherein:
FIG. 1 shows a bridge circuit of the prior art using N-type switches, monolithically integrated by utilizing a junction-type isolation technique;
FIG. 2 shows the same bridge circuit of FIG. 1 provided with a polarity guard diode, in accordance with a known technique;
FIG. 3 is a schematic perspective, sectional view of a junction-isolated integrated structure of an NPN transistor;
FIG. 4 is a schematic perspective, sectional view of a junction-isolated integrated structure of a PNP transistor;
FIG. 5 is an output bridge circuit modified in accordance with the present invention; and
FIG. 6 represents a different embodiment of the circuit of the present invention.
As it may be easily recognized by observing FIG. 4 in relation to what has been said before for the NPN integrated structure shown in FIG. 3, the integrated structure of a P-type transistor, such as the PNP transistors TP5 and TP6 of the circuits depicted, contrary to an N-type structure, is intrinsically protected against supply polarity inversion because the emitter region E is a P-type region which is isolated from the P-type substrate S by an N-type region (constituted by the buried layer and by the base epitaxial region B which are both N-type regions). Therefore there are series connected diodes having opposite polarity among each other (as schematically depicted on the cross section by means of the relative graphic symbols) which oppose the passage of current whichever the polarity of the supply voltage even if directly connected across the supply rails.
It has now been recognized possible to practically nullify the additional voltage drop across the polarity guard D3 by making a bridge circuit as shown in FIG. 5, i.e. by connecting directly to the positive supply rail the emitters of the two PNP transistors, TP5 and TP6, which drive the integrated NPN power switches, TN1 and TN2.
In fact, the total voltage drop of the bridge circuit of FIG. 5 is given by the greater one of the following pairs of expressions: (for a first diagonal),
.[.VCESAT (TP6)+VBE(TN2)+VCESAT (TN3).]. .Iadd.VCESAT (TP5)+VBE(TN1)+VCESAT (TN4) .Iaddend.
or (for the other diagonal),
VCESAT (TP6)+VBE(TN2)+VCESAT (TN3)
and (for the same first diagonal),
VF (D3)+VCESAT (TN1)+VCESAT (TN3)
or (for the other diagonal),
VF (D3)+VCESAT (TN2)+VCESAT (TN3).
The protection against an accidental inversion of polarity of the supply is ensured by the guard diode D3 while the voltage drop across the driving bridge circuit remains substantially similar to the voltage drop of the bridge circuit of FIG. 1 without the protection diode D3.
Through a correct dimensioning of the structures of the integrated devices which compose the bridge circuit the following conditions may be easily ensured:
(which indicatively is comprised between 0.6 and 1.2 V); and
VCESAT (TP5 and TP6)≈VCESAT (TN1 and TN2)
(which indicatively is comprised between about 0.3 and 1.0 V).
The simple solution proposed by the present inventors is applicable, as it will be obvious to the skilled technician, to different types of integrated devices, such as:
(a) monolithically integrated full-bridge circuit, comprising, beside the drive circuitry also the bipolar NPN power transistors TN1, TN2, TN3 and TN4 and the two drive PNP transistors TP5 and TP6;
(b) two monolithically integrated, half-bridge circuits, each comprising respectively the transistors TN1, TN3 and TP5 and the transistors TN2, TN4 and TP6;
(c) a double switch toward the positive supply rail comprising the power NPN transistors TN1 and TN2 and the relative drive PNP transistors TP5 and TP6, which circuit may be coupled to known circuits, either in a monolithic or discrete form, which implement the switches toward ground TN3 and TN4, utilizing either bipolar transistors or MOS transistors or SCR or other equivalent power devices.
For each of these integrated embodiment forms: (a), (b) and (c), the guard diode D3 against supply polarity inversion may be itself monolithically integrated if the particular fabrication process of the integrated circuit allows it or may be a discrete component whenever the overall design economy suggests it.
Notably the protection diode D3 will carry the same current as only one of the two power transistors TN1 or TN2 and never a current double of the latter current because simultaneous conduction of the integrated switches TN1 and TN2 is otherwise excluded by the drive circuitry.
An alternative embodiment of the circuit of the invention which is particularly preferred for integrated devices to be used in car equipments and in similar environments wherein high level spikes and "dump" voltage conditions are likely to occur on the supply, is shown in FIG. 6.
By replacing the diode D3 with an equivalent first Zener diode DZ3 and by connecting a second Zener diode ZP between the ground rail and the cathode of the Zener DZ3, as shown in FIG. 6, the transistors TP5 and TP6 will be effectively protected from negative and positive voltage spikes on the supply.
During normal operation conditions the forward biased Zener diode DZ3 is equivalent to a normal diode (D3 of FIG. 5). In presence of negative spikes on the supply, the current would flow through ZP, TN1 and TN2 in a forward conduction condition and through the reverse-biased Zener diode DZ3, which will maintain the voltage across the transistors TP5 and TP6 limited to the Zener breakdown voltage. In case of positive voltage spikes, the current will flow through DZ3 in a forward conduction condition and through the Zener diode ZP which will limit the voltage to the Zener breakdown or to the Zener breakdown voltage plus the forward voltage drop across the Zener diode DZ3.
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|U.S. Classification||361/84, 361/18|
|International Classification||H02H9/04, H02P7/00, H02H11/00|
|Cooperative Classification||H02H11/002, H02P7/0044, H02H9/047|
|European Classification||H02P7/00E1, H02H11/00C|