|Publication number||USRE36490 E|
|Application number||US 08/886,107|
|Publication date||Jan 11, 2000|
|Filing date||Jun 30, 1997|
|Priority date||Jul 21, 1988|
|Also published as||US5007025|
|Publication number||08886107, 886107, US RE36490 E, US RE36490E, US-E-RE36490, USRE36490 E, USRE36490E|
|Inventors||Sang Ki Hwang, Tae Sung Jung, Kyu Hyun Choi|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (2), Classifications (14), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a power and signal line bussing method for high density and high speed memory devices.
2. Description of the Prior Art
A conventional power line bussing method is shown in FIG. 1. Chip 1 has two memory cell arrays 2 centered around peripheral circuitry 4, which comprises multiple logic circuits. Power line 3a supplies power from Vcc pad to peripheral circuitry 4. Power line 3a runs from Vcc pad 5, around memory cell array 2, to peripheral circuitry 4. Ground line 3b electrically connects peripheral circuitry 4 with GND pad 5'. Ground line 3b runs from GND pad 5', around memory cell array 2, to peripheral circuitry 4.
However, employing a single power line 3a to couple power to peripheral circuitry 4 does not effectively reduce noise. To best reduce noise, a power line should be coupled independently to each circuit in peripheral circuitry 4. Yet, separating power line 3a further would increase the chip size because the area around memory cell arrays 2 would need to be engaged. Thus, the bussing arrangement according to the conventional bussing method is not conductive to noise reduction nor high density packing.
A conventional signal line bussing arrangement for chip 1 is shown In FIG. 2. Pad signal line 3', positioned around memory cell arrays 2, supplies signals from external pad 6 to peripheral circuit 4. Circuit signal line 3", also positioned around memory cell array 2, supplies signals from internal circuit 6' to peripheral circuitry 4.
However, signal line bussing according to this arrangement results in large signal delays because signals from pad 6 or internal circuit 6' must propagate the extra distance required to circumvent memory cell arrays 2.
A final disadvantage of conventional bussing arrangement arises inherently from the design. During conventional packaging processes, a passivation layer and an insulation layer are formed above the memory cell array. A final package material layer is then formed on top of the passivation layer. Yet, even with the passivation and insulation layers, radiation generated from the package material layer penetrates the memory cells and causes a soft (or operation) error. To prevent this soft error, am additional shield layer formed on the memory cell array is desired.
An object of the present invention is to provide am efficient power and signal bussing arrangement for high speed and high density memory arrays.
Another object of the present invention is to reduce chip noise generated in high speed memory devices without increasing chip size.
Still another object of the present invention is to provide a fast access time by eliminating excess path distance.
Yet another object is to provide an additional insulative layer above memory cells to reduce soft error.
To achieve these objects, power, ground and signal lines are formed directly above the memory cell array. The power and ground lines are parallel and positioned in an adjacent alternating pattern.
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only and are not to limit the present invention wherein:
FIG. 1 is a top view of a power line bussing method according to the prior art;
FIG. 2 is a top view of a signal line bussing method according to the prior art;
FIG. 3 is a top view of a power line bussing method according to the present invention; and
FIG. 4 is a top view of a signal line bussing method according to the present invention.
FIG. 3 shows a power line bussing arrangement according to the present invention. Chip 11 comprises two memory cell arrays 12 centered around peripheral circuitry 14. Power lines 13a, formed above memory cell arrays 12 and peripheral circuitry 14, supplies power from Vcc pad 15 to peripheral circuitry 14. Ground lines 13b, formed above memory cell arrays 12 and peripheral circuitry 14, connects peripheral circuitry 14 to GND pad 15'. Both power lines 13a and ground lines 13b are separated parallel lines traversing end-to-end chip 11. All power lines 13a are connected to Vcc pad 15 and all ground lines 13b are connected to GND pad 15'. Ground lines 13b and power lines 13a are formed in an adjacent alternating pattern such that a power line 13a is positioned adjacent to ground line 13b, which is positioned adjacent another power line 13a, and so on.
Accordingly, Vcc power is supplied through Vcc pad 15 and power lines 13 to each circuit in the peripheral circuitry 14. By coupling a power line independently to each circuit in peripheral circuitry 14, noise generated by these circuits is minimized.
Chip 11 further comprises external pad 16 and internal circuit 16'. Pad signal line 13', formed above memory cells 12, couples external pad 16 to peripheral circuitry 14. Circuit signal line 13", formed above memory cells 12, couples internal circuit 16' to peripheral circuitry 14.
The present invention Is advantageous to high speed memory devices. According to this bussing arrangement, signals carried by pad signal line 13' and circuit signal line 13" propagate directly to, and directly from, peripheral circuitry 14. Thus, propagation time is decreased, thereby improving chip speed.
The present invention is also advantageous for high density memory devices. Bussing the power, ground and signal lines directly across memory cell arrays, rather than around these arrays, reduces chip size by eliminating the area around the memory cell arrays.
Further, forming power lines 13a, ground lines 13b, and signal lines 13', 13" above memory cell arrays 12 provides an additional shield layer between memory cell arrays 12 and the package material layer. Thus, soft error is reduced.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4426689 *||Nov 28, 1980||Jan 17, 1984||International Business Machines Corporation||Vertical semiconductor integrated circuit chip packaging|
|US4439841 *||Jun 10, 1981||Mar 27, 1984||Fujitsu Limited||Semiconductor memory devices|
|US4791609 *||Apr 9, 1987||Dec 13, 1988||Nec Corporation||Semiconductor integrated circuit device|
|US4811288 *||Jun 24, 1986||Mar 7, 1989||Ncr Corporation||Data security device for protecting stored data|
|US4849943 *||Jul 24, 1987||Jul 18, 1989||U.S. Philips Corp.||Integrated memory circuit having a block selection circuit|
|JPS63100769A *||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7050321 *||Dec 31, 2002||May 23, 2006||Hynix Semiconductor Inc.||FeRAM having new signal line structure|
|US20040042252 *||Dec 31, 2002||Mar 4, 2004||Kang Hee Bok||FeRAM having new signal line structure|
|U.S. Classification||365/226, 365/51|
|International Classification||G11C11/41, H01L21/822, H01L27/04, H01L27/10, G11C11/401, G11C11/34, G11C5/02, G11C5/14|
|Cooperative Classification||G11C5/025, G11C5/14|
|European Classification||G11C5/14, G11C5/02S|