|Publication number||USRE36781 E|
|Application number||US 09/291,091|
|Publication date||Jul 18, 2000|
|Filing date||Apr 13, 1999|
|Priority date||Aug 2, 1995|
|Also published as||US5621340|
|Publication number||09291091, 291091, US RE36781 E, US RE36781E, US-E-RE36781, USRE36781 E, USRE36781E|
|Inventors||Thomas H. Lee, Kevin S. Donnelly|
|Original Assignee||Rambus, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (14), Referenced by (18), Classifications (15), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to comparator circuits and more particularly to differential comparator circuits that amplify small swing input signals to full swing output signals.
A differential comparator is often used in clock acquisition circuits such as delay-locked loops (DLL) and phase locked loops (PLL) to compare the value of a voltage at a first terminal of the differential comparator to the value of a voltage at a second terminal of the differential comparator. For some applications, the signals provided at the inputs of the differential comparator are "small swing" signals that have small amplitudes relative to the supply voltage levels. For example, for CMOS circuits wherein the supply voltage VCC is equal 3.3 volts and system ground VSS is equal to zero volts, a small swing signal may have an amplitude of 0.5 volts that swings between a low of 1.5 volts and a high of 2.0 volts. A "full swing" signal swings approximately between 3.3 volts and zero volts (ground).
Clock acquisition circuits are typically used to clock the circuitry of an integrated circuit, and the differential comparator must output full swing signals to drive the integrated circuit. The differential comparator circuit must therefore provide gain to amplify the small swing input signals to a full swing output signal. For higher frequency applications, it is difficult to provide the necessary gain using prior differential comparators.
Therefore, it is an object of the present invention to provide a differential comparator that amplifies small swing signals into full swing signals.
It is a further object of the present invention to provide a CMOS differential comparator that amplifies small swing input signals to full swing output signals at higher frequencies.
A differential comparator that amplifies small swing signals to full swing signals is described. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the complementary signals, wherein each inverter has a trip point voltage .[.equal.]. .Iadd.corresponding .Iaddend.to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals.
Because the outputs of the current switch center about the trip point voltage of the inverters, the inverters provide a current path between VCC and VSS during normal operation. According to one embodiment, the differential comparator includes circuitry for disabling the differential comparator during a power-down mode of operation such that the differential comparator draws little or no current. Part of this functionality is provided by designing the inverters to be tri-statable. The need for additional disabling circuitry for disabiling the current switch, is dictated by the circuit topology of the current switch.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description which follows below.
The present invention is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
FIG. 1 shows a differential comparator according to one embodiment.
FIG. 2 shows a voltage generator that supplies a trip point voltage VTR.
FIG. 3 shows a tri-statable inverter according to one embodiment.
FIG. 4 shows a differential comparator as including a bias circuit.
A differential comparator according to the present embodiments quickly amplifies small swing differential input signals to generate full swing complementary output signals. The differential comparator generally comprises an input stage, a gain stage, and an output stage. The gain stage generally comprises inverters each having a trip point voltage of VTR. The input stage acts as a current switch that outputs complementary output signals each having a voltage swing that centers about the trip point voltage VTR. Centering the output signals of the input stage about the trip point voltage VTR enables the inverters of the gain stage to switch on and off quickly to provide full swing output signals. The output stage provides additional gain.
FIG. 1 shows a differential comparator 100 according to one embodiment. Differential comparator 100 comprises an input stage 110, a gain stage 120, and an output stage 130 coupled in series. Input stage 110 accepts small swing differential input signals Vin+ and Vin-. The amplitude of the differential input signal Vin may be, for example, 0.5 volts. Input stage 110 provides a modest gain, and output signals of input stage 110 are provided via output nodes A and B to gain stage 120, which amplifies the output signals of the input stage 110 into full swing signals. Output stage 130 provides further gain, speeding the transitions between the rail voltages and providing sufficient output current to drive the capacitive load of the remaining portions of the integrated circuit.
Input stage 110 is shown as a common source differential amplifier that operates as a current switch wherein a current having a value of 2I1 is switched between the transistors of the differential amplifier. Alternative current switch and differential amplifier architectures may be used. Input stage 110 includes a differential pair of NMOS transistors 111 and 112, each having their sources coupled to system ground VSS via a common node N and current source 115 and their drains coupled to the supply rail VCC via current sources 113 and 114, respectively. Current sources 113 and 114 are each selected to source a current having a value of I1, and current source 115 is selected to sink a current having a value of twice I1. Output node A is taken at the drain of transistor 112, and output node B is taken at the drain of node 111.
Resistors R1 and R2 having equal values are coupled in series between output nodes A and B. A trip point supply voltage VTR is provided at the common node between resistors R1 and R2. The trip point supply voltage VTR causes the output voltages at output nodes A and B to center around the trip point supply voltage VTR. The output voltage at each output node of the input stage 110 is approximately (VTR ħI1 R), wherein R is the value of each of the transistors R1 and R2. Wherein Vin+>Vin-, the voltage at output node A is approximately (VTR +I1 R), and the voltage at output node B is approximately (VTR -I1 R). Conversely, wherein Vin+<Vin-, the voltage at output Node A is approximately (VTR -I1 R), and the voltage at output node B is approximately (VTR +I1 R).
Gain stage 120 comprises a first input inverter 121 having its input coupled to output node B and a second input inverter 122 having its input coupled to output node A. Both input inverters are CMOS inverters. The value of trip point supply voltage VTR is selected to be the value of the trip point voltage of input inverters 121 and 122 such that inverters 121 and 122 switch on and off quickly.
Because the output voltages of input stage 110 center about the trip point voltage of input inverters 121 and 122, input inverters 121 and 122 can change states quickly. Unfortunately, the MOS transistors of inverters 121 and 122 are never fully switched off. To reduce the power consumption of input inventers 121 and 122, input inverters 121 and 122 are tri-statable. Each input inverter therefore includes an enable input coupled to receive an enable signal EN for coupling and decoupling the inverters from the supply rails. The enable signal may be deasserted low, for example, when the integrated circuit and differential comparator are to be placed in a power-down mode wherein power consumption of differential comparator 100 is reduced. As will be described with respect to FIG. 4, differential comparator 100 draws no current when operating in the power-down mode.
Cross-coupled inverters 123 and 124 are provided to improve the power supply rejection of differential comparator 100. Disturbances in the power supplies of input inverters 121 and 122 may result in one of the output signals of the input inverters beginning to switch between rail voltages before the other output signal. Cross-coupled inverters 123 and 124 compensate for this effect. Inverter 123 has its input coupled to the output of input inverter 121 and its output coupled to the output of input inverter 122. Similarly, inverter 124 has its input coupled to the output of inverter 122 and its output coupled to the output of inverter 121. The cross-coupled inverters help to ensure that the differential output voltages of gain stage 120 cross approximately at the threshold voltage VTR.
Cross-coupled inverters 123 and 124 need not provide as much current as input inverters 121 and 122. Therefore, according to one embodiment, the channel widths of the CMOS transistors of cross-coupled inverters 123 and 124 are approximately 20% of the channel widths for input inverters 121 and 122. Cross-coupled inverters 123 and 124 may also be tri-statable.
Output stage 130 comprises inverters 131 and 132. The input of inverter 131 is coupled to the output of inverter 121, and the input of inverter 132 is coupled to the output of inverter 122. Output inverters 131 and 132 provide additional gain and provide sufficient current to drive the capacitive load of an integrated circuit coupled to the outputs of differential comparator 100. Output inverters 131 and 132 may also be tri-statable.
FIG. 2 shows a voltage generator 200 that supplies the trip point voltage VTR. According to the present embodiment, centering voltage generator 200 comprises an inverter 210 having the same operating characteristics as input inverters 121 and 122 wherein inverter 210 has its output coupled to its input. The use of matching inverter 210 makes the centering voltage generator 200 less susceptible to process variations that affect the trip point voltages of input inverters 121 and 122.
FIG. 3 shows a tri-statable inverter 300 according to one embodiment. Tri-statable inverter 300 generally comprises a CMOS inverter which includes a PMOS transistor 301 and an NMOS transistor 302 having their gates commonly coupled to an input node and their drains commonly coupled to an output node. The source of PMOS transistor 301 is coupled to VCC via PMOS transistor 303, and the source of NMOS transistor 302 is coupled to system ground VSS via NMOS transistor 304. The enable signal EN is coupled directly to the gate of transistor 304 and to the gate of transistor 303 via inverter 305 for removing the conductive path between VCC and VSS when it is desirable to reduce the power consumption of differential comparator 100. When the enable signal EN is logic low (deasserted), transistors 303 and 304 are switched off. Tri-stable inverter 300 operates as a normal CMOS inverter when enable signal EN is logic high (asserted). Enable signal EN may alternatively be provided as an active low signal.
FIG. 4 shows differential comparator 100 as further including a bias circuit 400 for ensuring proper current values of current sources 113, 114 and 115 and for switching off the current sources when differential comparator 100 is placed in the power-down mode. According to one embodiment, current sources 113 and 114 are matched PMOS transistors, and current source 115 is an NMOS transistor. Bias circuit 400 provides biasing current to the gates of transistors 113, 114 and 115 such that transistors 113-115 conduct the appropriate amount of source-drain current.
Bias circuit 400 generally comprises a pair of differential input transistors 411 and 412 that are approximately half the size of transistors 111 and 112 of input stage 110. The gates of transistors 411 and 412 are coupled to differential input voltages Vin+ and Vin-, respectively. The sources of transistors 411 and 412 are commonly coupled to VSS via NMOS transistor 415, which is approximately half the size of NMOS transistor 115 of input stage 110. NMOS transistor 416 has matching characteristics to transistor 415 and is coupled to receive an external bias current I1 from a current source 417, which may be a bandgap voltage generator. Transistor 416 is coupled in a current mirroring arrangement to the gate of transistor 415 such that transistor 415 sinks a current I1. The gate of transistor 115, which is twice the size of transistor 416, also has its gate coupled to the gate of transistor 416 such that transistor 115 sinks a current 2I1.
The drains of transistors 411 and 412 are commonly coupled to the drain of transistor 413. Transistor 413 has its gate commonly coupled to the gates of transistors 113 and 114 in a current mirroring arrangement such that the drain currents of transistor 113 and 114 are of the desired value.
Transistor 420 and inverter 421 are provided such that the current sources of input stage 110 are switched off to disable differential comparator 100 during power-down mode. Transistor 420 has its drain coupled to the gate of transistor 115, its source coupled to VSS, and its gate coupled to the output of inverter 421. Inverter 421 has its input coupled to receive enable signal EN. When the EN signal is deasserted low, the output of inverter 421 is high such that transistor 420 is switched on and the gate of transistor 115 is pulled towards ground. This results in all of the current sources 113, 114, and 115 of input stage 110 being switched off. Deasserting the EN signal also tri-states input inverters 121 and 122. Cross-coupled inverters 123 and 124 ensure that the inputs to inverters 131 and 132 are biased to a logic state. Thus, differential comparator 100 draws no current while operating in the power-down mode.
In the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3863080 *||Oct 18, 1973||Jan 28, 1975||Rca Corp||Current output frequency and phase comparator|
|US4110641 *||Jun 27, 1977||Aug 29, 1978||Honeywell Inc.||CMOS voltage comparator with internal hysteresis|
|US4249095 *||Feb 26, 1979||Feb 3, 1981||Rca Corporation||Comparator, sense amplifier|
|US4394587 *||May 27, 1981||Jul 19, 1983||Motorola, Inc.||CMOS Differential comparator with hysteresis|
|US4547685 *||Oct 21, 1983||Oct 15, 1985||Advanced Micro Devices, Inc.||Sense amplifier circuit for semiconductor memories|
|US4573022 *||Dec 13, 1984||Feb 25, 1986||Kabushiki Kaisha Toshiba||Semiconductor integrated circuit using vertical PNP transistors|
|US4739194 *||Nov 25, 1986||Apr 19, 1988||Tektronix, Inc.||Supergate for high speed transmission of signals|
|US5057788 *||Aug 28, 1990||Oct 15, 1991||Alps Electric Co., Ltd.||2-stage differential amplifier connected in cascade|
|US5077489 *||Oct 30, 1990||Dec 31, 1991||Sgs-Thomson Microelectronics S.R.L.||Comparator circuit implemented in the bipolar and mos technology|
|US5132640 *||Oct 4, 1990||Jul 21, 1992||Kabushiki Kaisha Toshiba||Differential current amplifier circuit|
|US5281865 *||Nov 26, 1991||Jan 25, 1994||Hitachi, Ltd.||Flip-flop circuit|
|US5289054 *||Mar 24, 1992||Feb 22, 1994||Intel Corporation||Fast electronic comparator|
|US5448200 *||Dec 18, 1991||Sep 5, 1995||At&T Corp.||Differential comparator with differential threshold for local area networks or the like|
|US5488321 *||May 16, 1995||Jan 30, 1996||Rambus, Inc.||Static high speed comparator|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6906557 *||Jun 30, 2000||Jun 14, 2005||Intel Corporation||Fuse sense circuit|
|US7183836||May 11, 2005||Feb 27, 2007||Intel Corporation||Fuse sense circuit|
|US7208994||May 11, 2005||Apr 24, 2007||Intel Corporation||Fuse sense circuit|
|US7215157 *||Jul 13, 2004||May 8, 2007||Matsushita Electric Industrial Co., Ltd.||Small-amplitude differential interface circuit|
|US7221210||May 11, 2005||May 22, 2007||Intel Corporation||Fuse sense circuit|
|US7332950||Jun 14, 2005||Feb 19, 2008||Micron Technology, Inc.||DLL measure initialization circuit for high frequency operation|
|US7498851 *||Jan 3, 2005||Mar 3, 2009||Nxp B.V.||High speed comparator|
|US8330446||Apr 18, 2012||Dec 11, 2012||Mediatek Inc.||Calibration apparatus and calibration method thereof|
|US8415979 *||Nov 4, 2010||Apr 9, 2013||Mediatek Inc.||Differential driver with calibration circuit and related calibration method|
|US8585675||Jan 29, 2011||Nov 19, 2013||The United States Of America As Represented By The Secretary Of The Army||Decision-assist method of resuscitation of patients|
|US20050083101 *||Jul 13, 2004||Apr 21, 2005||Matsushita Electric Industrial, Co., Ltd.||Small-amplitude differential interface circuit|
|US20050101907 *||Sep 8, 2004||May 12, 2005||Sondeen Jill L.||System and method for providing servo-controlled resuscitation|
|US20050200385 *||May 11, 2005||Sep 15, 2005||Parker Rachael J.||Fuse sense circuit|
|US20050212584 *||May 11, 2005||Sep 29, 2005||Parker Rachael J||Fuse sense circuit|
|US20060279342 *||Jun 14, 2005||Dec 14, 2006||Micron Technology, Inc.||DLL measure initialization circuit for high frequency operation|
|US20070116407 *||Jan 3, 2005||May 24, 2007||Koninklijke Philips Electronics N.V.||High speed comparator|
|US20090045862 *||Jul 2, 2008||Feb 19, 2009||Hynix Semiconductor, Inc.||Clock generating circuit of semiconductor memory apparatus|
|US20120112794 *||Nov 4, 2010||May 10, 2012||Kuan-Hua Chao||Differential driver with calibration circuit and related calibration method|
|U.S. Classification||327/65, 327/89, 327/374, 327/77|
|International Classification||H03F3/72, H03K5/24, H03K3/356|
|Cooperative Classification||H03F3/72, H03K5/2481, H03K3/356121, H03K5/249|
|European Classification||H03F3/72, H03K5/24F4, H03K3/356G2B, H03K5/24F2|
|Mar 22, 2001||SULP||Surcharge for late payment|
|Mar 22, 2001||FPAY||Fee payment|
Year of fee payment: 4
|Oct 20, 2008||REMI||Maintenance fee reminder mailed|
|Apr 15, 2009||LAPS||Lapse for failure to pay maintenance fees|