|Publication number||USRE37070 E1|
|Application number||US 09/249,497|
|Publication date||Feb 27, 2001|
|Filing date||Feb 12, 1999|
|Priority date||Nov 14, 1994|
|Also published as||US5604541|
|Publication number||09249497, 249497, US RE37070 E1, US RE37070E1, US-E1-RE37070, USRE37070 E1, USRE37070E1|
|Inventors||Dae-Jin Kim, Key H. Kim, Hee B. Park, Jung S. Park, Yung G. Kim|
|Original Assignee||Lg Electronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Non-Patent Citations (1), Referenced by (3), Classifications (15), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a high definition television (HDTV) receiver, and more particularly, to a HDTV receiver which is improved in its overall performance and is simplified in its configuration, by improving a symbol timing restoring circuit.
FIG. 1 is a block diagram of a conventional 8-vestigial sideband (VSB) receiver, in which a high-frequency signal input from an antenna (ANT) is demodulated and is carrier-restored when a channel is a selected in a tuner 1 and a signal having a central frequency of 44 MHz is automatic-gain controlled and IF-bandpass filtered in an IF processor & carrier restoring portion 2.
This signal is digitally sampled in an analog-to-digital conventer (ADC) 3 and precise symbol timing is detected by a timing restoring portion 4, thereby controlling the timing of ADC 3.
The output of ADC 3 is also input to a sync detector 5 to detect a data segment sync from a data segment sync pattern (FIG. 3A) and to detect a field sync from a field sync pattern being in the first line of a transmission format.
At this time, the data segment sync and field sync detected in sync detector 5 are used as the control signals of subsequent blocks 7 through 16.
NTSC (National Television System Committee) interference detector 7 receives a signal passing through a post-comb filter 6 and a signal not passing therethrough and determines whether there is an identical channel interference with that of NTSC or not, to then transmit a comb control signal SC1.
If there is no NTSC identical channel interference, the signal not passing through post-comb filter 6 is selected by a multiplexer 8. A channel equalizer 9 equalizes the incoming signal which is set to 8 levels to remove the intersymbol interference due to a ghost generated at the channel.
Also, a phase corrector 10 corrects the phase error remaining after signal-processing, setting the incoming signal to 8 levels. An optimal viterbi decoder 11 performs a 4-state viterbi decoding operation and the decoded output is output through multiplexer 13.
If there is NTSC identical channel interference, the output of post-comb filter 6 is selected as the output of multiplexer 8. At this time, post-comb filter 6 subtracts data delayed for 12 symbol period from the current data.
Therefore, the original 8 level data becomes 15 level data. The NTSC identical channel interference is removed. At this time, channel equalizer 9 and phase controller 10 operate assuming that the incoming signal is 15 level data, and multiplexer 13 selects and outputs the output of a partial response (PR) viterbi decoder 12.
PR viterbi decoder 12, an 8-state decoder, has much more complex structure than that of optimal viterbi decoder 11.
The output of multiplexer 13 is dissipated in order to enhance the correction capability for burst errors in a deinterleaver 14. An error controller 15 performs a Reed-Solomon decoding operation.
Also, a derandomizer 16 releases a signal randomly formed in a transmission port reversely. Timing restoring portion 4 is constituted by a data segment sync detector 4 a and a phase locked loop (PLL) 4 b, as shown in FIG. 2. The digitally converted signal is concurrently output to data segment sync detector 4 a and PLL 4 b.
At this time, data segment sync detector 4 a detects a data segment sync, based on the data pattern “1001” for 4 symbol period of 2 levels shown in FIG. 3A.
PLL 4 b detects the phase error for the timing from a data segment sync pattern. The output of a phase detector is as shown as FIG. 3B, digitally, and as FIG. 3C, analogically.
The position of a sampling point 4 shown in FIG. 3C is a zero-crossing point, and a symbol timing is detected using the zero-crossing point.
However, the aforementioned conventional art adopting a post-comb filter for reducing the NTSC identical channel interference has a very complex configuration.
To solve these problems, it is an object of the present invention to provide a HDTV receiver, which allows a better symbol timing restoration even if there is an NTSC identical channel interference, by improving a symbol timing restoring circuit, and which is simplified in its configuration, by eliminating a post-comb filter.
To accomplish the above object, there is provided a HDTV receiver comprising: a tuner for selecting a necessary channel from input signals via an antenna; an IF processing & carrier restoring portion for performing an IF process & carrier restoration from the output of the tuner; an analog-to-digital converter (ADC) for converting the output of the IF processing & carrier restoring portion into a digital signal; a timing restoring portion for restoring a timing from the output of the ADC; a 2:1 down-sampler for 2:1 down-sampling the output of the ADC; a sync detector for detecting a sync from the output of the 2:1 down-sampler; a channel equalizer for performing a channel equalization from the output of the 2:1 down-sampler; a phase controller for correcting the phase error from the output of the channel equalizer; an optimal viterbi decoder for performing a viterbi decoding operation from the output of the phase controller; a deinterleaver for dissipating the output of the optimal viterbi decoder in order to enhance the correction capability due to burst errors; an error controller for performing a Reed-Solomon decoding operation with respect to the output of the deinterleaver; and a derandomizer for releasing the output of the error controller and restoring a signal randomly formed at a transmission port reversely.
The above objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:
FIG. 1 is a block diagram of a conventional HDTV receiver;
FIG. 2 is a detailed block diagram of a timing restoring portion shown in FIG. 1;
FIGS. 3A through 3C are timing charts shown in FIG. 2;
FIG. 4 is a block diagram of a HDTV receiver according to the present invention; and
FIG. 5 is a detailed block diagram of a timing restoring portion shown in FIG. 4.
As shown in FIG. 4, the HDTV receiver according to the present invention has a simpler configuration than the conventional system in that post-comb filter 6, NTSC interference detector 7, multiplexer 8, PR viterbi decoder 12 and multiplexer 13 are eliminated from the conventional one. Channel equalizer 9 and phase corrector 10 of the convention system correspond to channel equalizer 107 and phase controller 108 of the present invention, respectively. Timing restoring portion 4 of the convention system corresponds to a new timing restoring portion 104 of the present invention, so that a symbol timing restoration is performed well even in the case of the NTSC identical channel interference.
As shown in FIG. 5, timing restoring portion 104 includes an FIR filter 113 for filtering only the signal of a necessary symbol rate among the signals passing through ADC 103, a phase error detector 114 for detecting an phase error (ek) from the output of FIR filter 113, a digital-to-analog converter (DAC) 115 for converting again the output of phase error detector 114 into an analog signal, a lowpass filter 116 for lowpass-filtering the output of DAC 115, and a voltage controlled oscillator 117 for varying an oscillated frequency according to the output of lowpass filter 116 to supply a signal required in ADC 103.
At this time, phase error detector 114 is constituted by ½ symbol rate delays 114 a and 114 b for delaying the output of FIR filter 113 by ½ symbol rate, an adder 114 c for adding the output of FIR filter 113 with the output of ½ symbol rate delay 114 b, and a multiplier 114 d for multiplying the output of adder 114 c with the output of ½ symbol rate delay 114 a to output a phase error (ek).
In the present invention having the aforementioned configuration, the operation of a tuner 101 and an IF processing & carrier restoring portion is the same as that of the conventional art. ADC 103 uses a clock of 21.52 MHz for over-sampling twice the symbol rate with a sampling clock, which is because the data twice over-sampled is required in timing restoring portion 104.
The signal restored from timing restoring portion 104 is directly supplied to 2:1 down-sampler 105, and 2:1 down-sampler 105 samples only the data of a desired symbol rate. A sync detector 106 detects a data segment sync and a data field sync.
A channel equalizer 107 to which only 8 level data is applied equalizes in accordance therewith. Also, phase controller 108 and optimal viterbi decoder 109 to which only 8 level data are applied, operate irrespective of 15 level data.
The operations of deinterleaver 110, error controller 111 and derandomizer 112 will be omitted here, since the respective elements operate in the same manner as that of the corresponding elements of the conventional system.
The signal passing through ADC 103 undergoes a bandpass filtering operation of central 5.38 MHz (=½T, here, 1/T is symbol rate) in FIR filter 113 of timing restoring portion 104.
The output of FIR filter 113 is delayed in ½ symbol rate delays 114 a and 114 b by ½ symbol rate. The output of ½ symbol rate delay 114 b and the output of FIR filter 113 is added in an adder 114 c. The added output and the output of ½ symbol rate delay 114 a is multiplied in a multiplier 114 d to then output a phase error (ek).
A phase error (ek) is converted into an analog signal in DAC 115 and is lowpass-filtered in a low-pass in lowpass filter 16. Then, voltage-controlled oscillator (VC) 117 supplies a clock required for DAC 103.
In other words, the signal passing through timing restoring portion 104 becomes a symmetric IF bandpass filtered signal of central 5.38 MHz. A zero crossing always occurs at a position of odd number times of T/2.
As described above, according to the the present invention, a symbol timing restoration is done well even if there is an NTSC identical channel interference, by improving a symbol timing restoring circuit. Also, based on the improved symbol timing restoring circuit, a post-comb filter can be eliminated, which considerably simplifies the overall circuit configuration.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4503453 *||Jul 19, 1982||Mar 5, 1985||Thomson-Csf||Digital method and device for correcting the phase error of a sampled signal as applicable to the correction of television signals|
|US5363408 *||Mar 24, 1992||Nov 8, 1994||General Instrument Corporation||Mode selective quadrature amplitude modulation communication system|
|US5425060 *||Jan 25, 1993||Jun 13, 1995||Harris Corporation||Mechanism for reducing timing jitter in clock recovery scheme for blind acquisition of full duplex signals|
|US5479449 *||May 4, 1994||Dec 26, 1995||Samsung Electronics Co. Ltd.||Digital VSB detector with bandpass phase tracker, as for inclusion in an HDTV receiver.|
|US5535252 *||Mar 22, 1994||Jul 9, 1996||Kabushiki Kaisha Toshiba||Clock synchronization circuit and clock synchronizing method in baseband demodulator of digital modulation type|
|1||*||"VSB Transmission System", Zenith Electronics Corporation, Dec. 17, 1993, pp 8-16, FIGS. 9, 12, 14.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7661120||Nov 26, 2003||Feb 9, 2010||Wegener Communications, Inc.||Automated transport stream apparatus and method|
|US20050114890 *||Nov 26, 2003||May 26, 2005||Wegener Communications, Inc.||Automated transport stream apparatus and method|
|US20100211985 *||Jan 5, 2010||Aug 19, 2010||Wegener Communications, Inc.||Automated transport stream remapping apparatus and method|
|U.S. Classification||348/426.1, 375/371, 348/538, 348/726, 375/355|
|International Classification||H04L7/033, H04N5/44, H04N5/04|
|Cooperative Classification||H03M13/41, H04N5/4401, H04L7/0334, H04N5/04|
|European Classification||H04L7/033D, H04N5/44N, H04N5/04|
|Jul 4, 2004||FPAY||Fee payment|
Year of fee payment: 8
|Aug 13, 2008||FPAY||Fee payment|
Year of fee payment: 12