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Publication numberUSRE37124 E1
Publication typeGrant
Application numberUS 09/096,693
Publication dateApr 3, 2001
Filing dateApr 27, 1994
Priority dateApr 30, 1993
Also published asDE69404255D1, DE69404255T2, DE69404935D1, DE69404935T2, DE69421035D1, DE69421035T2, DE69426498D1, DE69426498T2, EP0648386A1, EP0648386B1, EP0648387A1, EP0648388A1, EP0648388B1, EP0648389A1, EP0648389B1, EP0749207A2, EP0749207A3, EP0749207B1, US5525938, US5602514, US5635866, US5635877, WO1994026025A1, WO1994026026A1, WO1994026027A1, WO1994026028A1
Publication number09096693, 096693, US RE37124 E1, US RE37124E1, US-E1-RE37124, USRE37124 E1, USRE37124E1
InventorsTrevor K. Monk, Andrew M. Hall
Original AssigneeStmicroelectronics Limited
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Ring oscillator using current mirror inverter stages
US RE37124 E1
Abstract
A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.
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Claims(25)
We claim:
1. A ring oscillator comprising:
a plurality of oscillator stages, each stage comprising first and second transistors, wherein the first transistor has a controllable path connected between an output node and a reference voltage and a control node acting as an input node to the stage and wherein the second transistor has a controllable path connected between the output node and the reference voltage and a control node connected to the output node, the gain of each stage being selectively determined by the ratio of the widths of the first and second transistors to produce an output signal having a sawtooth or trapezoidal waveform and each stage further comprising a respective current source which controls the speed of the stage and which is connected to said output node, wherein the input node of one stage is connected to the output node of a preceding stage to form said ring oscillator and wherein the number of stages is selected so that there is a total phase shift of 360° around the ring at the frequency of operation.
2. A ring oscillator according to claim 1, wherein the first and second transistors are n-channel field effect devices having a gate as the control node and a source/drain path as the controllable path.
3. A ring oscillator according to claim 1, wherein the first and second transistors are bipolar transistors in which the base is the control node and the controllable path extends between a collector and emitter.
4. A ring oscillator according to claim 1, wherein the current source comprises a p-channel MOS field effect transistor gated by a control voltage.
5. A ring oscillator according to claim 2 wherein the current source comprises a p-channel MOS field effect transistor gated by a control voltage.
6. A ring oscillator according to claim 3 wherein the current source comprises a p-channel MOS field effect transistor gated by a control voltage.
7. A ring oscillator having improved process tolerance characteristics, said ring oscillator comprising:
a plurality of oscillator stages, each stage having a gain, a speed, and an operation frequency wherein an input node of one stage is coupled to an output node of a preceding stage to form a ring, and wherein the number of stages is selected so there is a total phase shift of 360° around the ring at the operation frequency, each stage including:
a first transistor having a control node, and a path controlled by the control node, the path coupling a reference voltage to the output node of said stage, wherein the control node is coupled to the input node of said stage;
a second transistor having a control node coupled to the output node of said stage and a controllable path which couples the reference voltage to the output node,
wherein the gain of said stage is selectively determined by the ratio of widths of said first transistor and said second transistor, and wherein an output signal of the stage is at least one of a sawtooth waveform and a trapezoidal waveform; and
a current source, which controls the speed of the stage, coupled to the output node.
8. An oscillator for producing a periodic waveform, the oscillator comprising:
a first, a middle, and a last serially coupled stage, each stage having an input terminal and an output terminal and the output terminal of the last stage coupled to the input terminal of the first stage, at least one stage including:
an input transistor coupled between the output terminal and a reference voltage, and having a control terminal coupled to the input terminal,
a second transistor coupled between the output terminal and the reference voltage, and having a control terminal coupled to the output terminal,
a current source coupled to the output terminal, and
wherein a ratio of the gain of the input transistor to the second transistor is greater than 2.
9. The oscillator of claim 8 wherein the input and second transistors comprise respective MOS transistors and wherein a drain of the input transistor is coupled to the output terminal, a gate of the input transistor is coupled to the input terminal, and wherein both a drain and gate of the second transistor are coupled to the output terminal.
10. The oscillator of claim 9 wherein the input and second transistors have respective first and second widths, wherein the ratio of the first width to the second width is greater than 2.
11. The oscillator of claim 8 wherein the input and second transistors comprise respective bipolar transistors and wherein a collector of the input transistor is coupled to the output terminal, a base of the input transistor is coupled to the input terminal, and wherein both a collector and base of the second transistor are coupled to the output terminal.
12. The oscillator of claim 11 wherein the ratio of the gain of the input transistor to the second transistor is a ratio of an area of the input transistor to the area of the second transistor.
13. The oscillator of claim 8 wherein the ratio is at least 2.5.
14. The oscillator of claim 8 wherein the ratio is selected such that at least one of the stages produces a sawtooth waveform at its output terminal.
15. The oscillator of claim 8 wherein the ratio is selected such that at least one of the stages produces a trapezoidal waveform at its output terminal.
16. The oscillator of claim 8 wherein the current source comprises a PMOS transistor having a drain coupled to the output terminal and having a gate coupled to a control voltage.
17. The oscillator of claim 8 wherein the current source comprises a bipolar transistor having a base coupled to a control voltage.
18. The oscillator of claim 8 wherein the speed of the at least one stage is controlled by the current source.
19. An oscillator for producing a periodic waveform, the oscillator comprising:
at least three stages each having an input terminal and an output terminal, wherein the input terminal of each stage is coupled to the output terminal of another stage so as to constitute a ring, at least one stage including:
an input transistor coupled between the output terminal and a supply voltage, and having a control terminal coupled to the input terminal,
a second transistor coupled between the output terminal and the supply voltage, and having a control terminal coupled to the output terminal,
a current source coupled to the output terminal, and
wherein a gain of the at least one stage is approximately 2.
20. The oscillator of claim 19 wherein the input and second transistors comprise respective MOS transistors and wherein a drain of the input transistor is coupled to the output terminal, a gate of the input transistor is coupled to the input terminal, and wherein both a drain and gate of the second transistor are coupled to the output terminal.
21. The oscillator of claim 20 wherein the input and second transistors have respective first and second widths, wherein the ratio of the first width to the second width is greater than 2.
22. The oscillator of claim 19 wherein the input and second transistors comprise respective bipolar transistors and wherein a collector of the input transistor is coupled to the output terminal, a base of the input transistor is coupled to the input terminal, and wherein both a collector and base of the second transistor are coupled to the output terminal.
23. The oscillator of claim 22 wherein the ratio of area of the input transistor to the second transistor is greater than 2.
24. The oscillator of claim 19 wherein the gain is selected such that at least one of the stages produces a sawtooth waveform at its output terminal.
25. The oscillator of claim 19 wherein the gain is selected such that at least one of the stages produces a trapezoidal waveform at its output terminal.
Description
FIELD OF THE INVENTION

This invention relates to an oscillator and more particularly to a ring oscillator.

BACKGROUND OF THE INVENTION

New manufacturing processes and new applications are forcing power supplies to lower voltages (3.3 v now, with 2.4 v and 1.5 v being expected soon). Advanced Phase-Locked Loops require stable oscillators which may be varied in frequency by a control signal.

To help achieve frequency stability, oscillators integrated into a noisy VLSI environment often use a regulator to generate a quiet power supply. This usually has to be at an even lower voltage than the normal power supply.

There is thus a desire to provide oscillators which can work at these very low supply voltages and still produce high quality, high frequency output signals.

Reference is made to IBM Technical Disclosure Bulletin, Vol. 31, No. 2, July 1988, pages 154 to 156 “CMOS Ring Oscillator with controlled frequency” which describes a ring oscillator using CMOS transistors and is designed to give an almost sinusoidal output. This design suffers from stability problems outside a narrow range of frequencies. In particular, as the frequency increases, the amplitude decreases and it becomes difficult to convert the signal to CMOS levels.

SUMMARY OF THE INVENTION

According to the present invention there is provided a ring oscillator comprising a plurality of oscillator stages, each stage comprising a first and second transistors. The first transistor has a controllable path connected between an output node and a reference voltage and a control node acting as an input node to the stage. The second transistor has a controllable path connected between the output node and the reference voltage and a control node connected to the output node. The gain of each stage is selectively determined by the ratio of the widths of the first and second transistors to produce an output signal having a sawtooth or trapezoidal waveform. Each stage further comprise a respective current source which controls the speed of the stage and which is connected to the output node. The input node of one stage is connected to the output node of a preceding stage to form a ring and the number of stages is selected so that there is a total phase shift of 360° around the ring at the frequency of operation.

For transistors of the same length, the width of the first transistor can be set to m times the width of the second transistor where m>1 to determine the d.c. gain of the stage. This ratio m determines the shape of the waveform output by the oscillator. The higher the value of m, the more the waveform moves away from a sinusoid. For a three stage oscillator, a ratio of m close to 2 produces a substantially sinusoidal output. The present invention uses a ratio higher than 2 and preferably with a minimum value of 2.5. In practice the smallest value that can be selected to provide an appropriately shaped waveform will be selected. The maximum value of m is limited by practical considerations and particularly layout considerations. A practical maximum value for m is likely to be about 10.

The first and second transistors can be n-channel field effect devices having a gate as the control node and the source-drain path as the controllable path. As the transistors are of the same type, process variations affect the transistors in the same manner. The maximum frequency of operation is limited only by the ratio of gain to gate capacitance.

The current source can comprise a p-channel transistor gated by a control voltage.

The first transistor is preferably operated in its saturation region.

The current sources of each stage can either be controlled by a common control signal or by respective different control signals.

The present oscillator can operate at voltages down to a level just above the threshold voltages of the transistors.

For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a low-voltage inverting gain stage in MOS technology;

FIG. 1a is a circuit diagram of an implementation of a current source;

FIG. 2 is a circuit diagram of a low-voltage inverting gain stage in bipolar technology;

FIG. 3 is a diagram showing the transistor structure of a ring oscillator;

FIG. 4 is an equivalent logical schematic for FIG. 3; and

FIG. 5 shows typical waveforms for the 3-stage ring oscillator of FIGS. 3 and 4.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 shows a low-voltage inverting gain stage in MOS technology. The stage comprises first and second transistors T1, T2 which have their drains connected together and their sources connected to ground. The gate of the first transistor T1 acts as the input Sin for the stage and the gate of the second transistor T2 acts as the output Sout. The gate of the second transistor T2 is connected to its drain. Each stage is controlled by a control current I which is generated by a current source 2. The current source 2 is connected between a supply voltage Vcc and the drains of the first and second transistors T1,T2. The common node between the current source 2 and the drains of the transistors T1 and T2 is denoted 4. As shown in FIG. 1a, the current source 2 can comprise a p-channel MOS field effect transistor T3 with its source/drain path connected between the supply voltage Vcc and the node 4 and its gate connected to receive a control signal V which is taken with respect to the supply voltage Vcc. In the following discussion, it will readily be apparent that where reference is made to the control current I, this can be taken in practice as being derived from the control voltage V. The stage also has capacitance C, the largest component of which is the gate capacitance of the transistors connected to the output Sout.

The ratio of gains of the transistors T1,T2 is indicated as “m”. The value of m controls the relative charge and discharge rates of the output mode Sout, and thus determines the gain of the stage. The speed of the stage (and thus the phaseshift at the frequency of operation) is readily controlled by varying the current I supplied by the current source 2.

FIG. 2 shows the low-voltage inverting gain stage in bipolar technology. This also has excellent low-voltage operation characteristics and the speed can be controlled using a current source 2 in precisely the same way. Although the rest of this specification refers to MOS circuits, it should be understood that the same idea can easily be applied to bipolar technology.

In FIG. 2, the first and second transistors are denoted Ti′ and T2′ and are connected in the same way as for FIG. 1, where gates correspond to bases, drains correspond to collectors and sources correspond to emitters.

FIG. 3 illustrates a 3-stage ring oscillator, the three stages being denoted S1,S2,S3. Each stage S1,S2,S3 is as illustrated in FIG. 1. Of course, a similar ring oscillator could be produced using the stages of FIG. 2. FIG. 4 shows the ring oscillator in an equivalent logical schematic. Each stage is a so-called single-ended stage, that is with a single input and a single output and is inverting. As is well known in the design of ring oscillators, for oscillation to occur it can be shown that there must be:

(i) an odd number n of stages

(ii) minimum of three stages

(iii) if all stages are identical and have a gain ratio of “m”, then

m>1/cos(pi/n)

where

pi=3.14 . . .

n=number of stages

and

m=gain of each stage

For a 3-stage ring, the formula above gives m>2.

Where the transistors are of the same length, the gain m=W(T1)/W(T2), where W is the width of a transistor.

Thus, by use of an appropriate layout, the parameter m can be made substantially independent of manufacturing process variables which would tend to affect the width of both transistors by corresponding amounts.

The required value for m, and hence the transistor sizes, is selected to satisfy small signal and large signal design requirements to provide a sawtooth or trapezoidal waveform. A system designed to produce these waveforms produces a more stable output amplitude from the oscillator across all operating frequencies. A more stable amplitude over a wide range of operating frequencies provides a signal which can be more reliably and easily converted to CMOS levels over a wide range of frequencies.

FIG. 5 shows the waveforms for the 3-stage oscillator of FIG. 4 when m=3. Node 1, node 2 and node 3 are denoted N1, N2 and N3 in FIG. 4.

The frequency of oscillation of the ring can be controlled by the control current I. In a symmetrical arrangement, each stage has the same phase shift at the frequency of operation (equal to 180°/n for inverting stages) and receives a common control signal so that the control currents I are the same. However, the phase shift can differ for each stage provided that the complete phase shift in the loop is 360° at the frequency of oscillation. In this case, the control currents I for the individual stages can be independently varied.

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Non-Patent Citations
Reference
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Referenced by
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US7719343 *Sep 8, 2003May 18, 2010Peregrine Semiconductor CorporationLow noise charge pump method and apparatus
US8378736Apr 27, 2010Feb 19, 2013Peregrine Semiconductor CorporationLow noise charge pump method and apparatus
US8686787May 11, 2011Apr 1, 2014Peregrine Semiconductor CorporationHigh voltage ring pump with inverter stages and voltage boosting stages
Classifications
U.S. Classification331/57, 327/281, 327/288, 327/285, 327/278, 331/177.00R, 331/108.00R
International ClassificationH03K5/00, H03K3/282, H03K3/354, H03K3/0231, H03K5/151, H03K3/03, H03K5/13
Cooperative ClassificationH03K3/0231, H03K2005/00202, H03K3/0322, H03K5/00006, H03K3/354, H03K3/03, Y10S331/03, H03K5/132, H03K5/133, H03K5/151
European ClassificationH03K5/00C, H03K5/151, H03K3/0231, H03K3/354, H03K5/13D, H03K3/03, H03K5/13D2, H03K3/03D2
Legal Events
DateCodeEventDescription
Nov 18, 2002ASAssignment
Owner name: STMICROELECTRONICS, INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS LIMITED;REEL/FRAME:013496/0067
Effective date: 20021030
Owner name: STMICROELECTRONICS, INC. 1310 ELECTRONICS DRIVE MA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS LIMITED /AR;REEL/FRAME:013496/0067