|Publication number||USRE37637 E1|
|Application number||US 09/433,094|
|Publication date||Apr 9, 2002|
|Filing date||Nov 3, 1999|
|Priority date||Apr 19, 1996|
|Also published as||EP0802507A2, EP0802507A3, US5719437|
|Publication number||09433094, 433094, US RE37637 E1, US RE37637E1, US-E1-RE37637, USRE37637 E1, USRE37637E1|
|Inventors||Mark Bradford Clifton, Richard Michael Flynn, Fred William Verdi|
|Original Assignee||Lucent Technologies Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Referenced by (55), Classifications (12), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Related subject matter is disclosed in the co-pending, commonly assigned U.S. patent application of E. Suhir—1, Ser. No. 08/551,241, filed on Oct. 31, 1995, entitled “Data Carriers Having An Integrated Circuit Unit”, in the co-pending, commonly-assigned U.S. patent application of Clifton-Flynn-Verdi 4-6-15, Ser. No. 08/558,579, filed on Oct. 31, 1995, entitled, “Smart Card Having a Thin Die”, and in U.S. Pat. No. 5,480,842 issued on Jan. 2, 1996 to Clifton, Flynn, and Verdi.
1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly to semiconductor die that are used in the manufacture of smart cards.
2. Background Art
Existing smart cards may fail when, due to applied mechanical stress, the semiconductor die of the smart card breaks. Mechanical stress is inherent in typical smart card operational environments, such as point-of-sale terminals, electronic cash machines, credit card reading devices, wallets, pockets, and purses. Semiconductor die strength is a significant factor in determining the overall durability and reliability of a smart card. Die thickness affects the ability of a semiconductor die to withstand flexure and applied mechanical force.
In the field of semiconductor fabrication, skilled artisans attempt to use the thickest semiconductor die that will fit within a smart card package. This approach is based upon an assumption that die strength is proportional to die thickness. Since existing smart card packages are approximately 0.030 inches thick, this dimension places a constraint on the maximum thickness of the semiconductor die which will fit within the package. To this end, note that it is not feasible to use semiconductor die that are about 0.030 inches thick. In addition to the die itself, the space within the smart card package is also occupied by lead terminations, structures that protect the die and/or the leads, labeling, magnetic striping, and discrete circuit components. Therefore, die thickness on the order of 0.011 inches are employed, representing the maximum die thickness that can easily fit within a smart card package. Semiconductor die thinner than 0.011 inches are typically not used in smart cards, as such die have traditionally been difficult to handle during the manufacturing process, and the resulting manufacturing expenses are relatively high. Furthermore, conventional wisdom dictates that, as the thickness of a die is decreased, the die become increasingly vulnerable to mechanical failure.
A shortcoming of existing 0.011-inch die is that the die do not provide sufficient immunity to mechanical flexure. When such die are used to fabricate smart cards, breakage and card failure may result if the smart card user bends or flexes the card. Accordingly, flexure is an especially important physical property to consider for smart card applications. In order to improve performance in this area, existing approaches have focused on strengthening the 0.011-inch die through the optimization of specific individual design parameters, such as grinding parameters, dicing parameters, and others. As opposed to integrating these design parameters into a broad-based design solution, typical approaches have adopted a piecemeal approach by considering the effects of only one or two design parameters on flexure resistance. For example, in material systems having high thermal coefficients of expansion, design parameters have been optimized for the purpose of increasing die tolerance to severe thermal transient conditions.
Another shortcoming of existing smart card semiconductor die designs is that little, if any, consideration is given to RF (radio frequency) performance issues. For example, one presently-available smart card requires direct mechanical and electrical contact during use, whereas another type of smart card uses signals in the extremely-low-frequency (ELF) area of the RF spectrum, in the range of 300 to 20,000 Hz, with existing industry-standard UART protocols of 2400, 4800, 9600, and/or 19,200 band. Existing smart cards do not operate at frequencies above the ELF region. Although transponder devices and pagers have been developed for use at higher frequencies, such devices occupy a much larger physical volume than is available within the confines of a smart card. Meanwhile, in relatively recent times, high-speed microprocessors operating at speeds of around 100 Mhz have been developed, and radio frequencies in the 800 and 900-Mhz regions of the frequency spectrum are now enjoying widespread use.
Consider a two-inch lead used in an existing smart card package. This lead provides negligible inductive reactance at 1 Khz, on the order of a fraction of an ohm. That same lead, used at 500 Mhz, provides an inductive reactance of several hundred ohms, which may severely disrupt desired circuit operations at higher frequencies. Moreover, when an existing semiconductor dice having a thickness of 0.011 inches is used to fabricate active semiconductor device, these devices provide electron transit times on the order of several tenths of microseconds, effectively limiting device operation to frequencies less than about 10 Mhz.
Existing field-effect transistors for use in the UHF and microwave regions of the RF spectrum use die thicknesses in the order of 0.00236 inches, so as to provide a relatively short electron transit time. These short electron transit times provide increased high-frequency performance. One technique for fabricating these field-effect transistors is described in U.S. Pat. No. 5,163,728 issued to Miller and entitled, “Tweezer Semiconductor Die Attach Method and Apparatus”. Unfortunately, the methods and systems described in the Miller patent are only practical when used to construct discrete transistor devices. The use of tweezer-based devices to construct smart cards is impractical because it would be much too labor-intensive, time-consuming, and expensive. What is needed is an improved technique for constructing a smart card that has enhanced RF (radio frequency) properties.
Smart card packages are about 0.030 inches thick, thereby providing a package that is very similar in dimensions to that of a conventional credit card. Note that existing smart card packaging techniques place the semiconductor die near the surface of the card, due to tight packaging and interconnect requirements, and also because the thickness of the die represents a substantial portion of the thickness of the actual smart card package. Therefore, if a user bends a smart card back and forth, the semiconductor die, being situated near the surface of the card, is subjected to relatively high levels of mechanical stress.
Improved smart card semiconductor die are provided that have a thickness of approximately 0.004 to 0.007 inches. These die are positioned at or near the neutral plane (i.e., plane of substantially zero mechanical strain during flexure) of a smart card, thereby providing smart cards having improved resistance to mechanical flexure and/or enhanced performance at RF frequencies.
FIG. 1 is a cross-sectional view of a prior art smart card semiconductor die;
FIG. 2 is a cross-sectional view of a thin smart card semiconductor die fabricated in accordance with a first embodiment disclosed herein;
FIG. 3 is a cross-sectional view of a thin smart card semiconductor die fabricated in accordance with a second embodiment disclosed herein;
FIG. 4 is a table comparing various physical parameters of the smart card semiconductor die shown in FIGS. 1, 2, and 3.
FIG. 5 is a cross-sectional view of the smart card semiconductor die of FIG. 2 in a state of mechanical flexure; and
FIG. 6 and FIG. 7 are a plan view of a smart card showing representative locations for various smart card components.
Existing die strength improvement techniques have not adequately addressed applications involving mechanical die flexure. In the context of smart card semiconductor die, during mechanical flexure, the mechanical stresses are greatest near the card surface, and are at a minimum value along a neutral plane within the body of the smart card. The neutral plane of the smart card may be defined as the plane of no strain during mechanical flexure of the smart card. If it is assumed that the smart card package is of a substantially uniform composition throughout, with no internal cavities, this neutral plane is at a depth approximately equal to half the thickness of the smart card, i.e., the “mid-plane” of the smart card. However, as a practical matter, the smart card package must contain a cavity for accommodating the semiconductor die. Additionally, stickers, laminates, and/or other types of dressing materials may be applied to the surface of the smart card for identification or ornamentation. These cavities, laminates, and/or stickers may shift the location of the neutral plane to a location that is not approximately equal to half the thickness of the smart card. However, the location of the neutral plane may be determined empirically, and/or with resort to mathematical calculations well-known to those skilled in the art.
Since the mechanical stresses are substantially zero at any point on the neutral plane, it would be desirable to position the semiconductor die at or near the neutral plane. However, even if an existing 0.011 inch die is centered along the neutral plane, the sheer thickness of the die itself results in portions of the die being located in higher stress regions near the surface of the card. Note that the thickness of a smart card must be limited to about 0.030 inches if the smart card is to physically resemble a conventional credit card. In order to provide physical space within the 0.030-inch-thick smart card package for electrical connections to a semiconductor die that is 0.011 inches thick, the semiconductor die must be mounted relatively close to a surface of the smart card.
It is generally difficult or impossible to situate a conventional 0.011-inch-thick semiconductor die on or near the neutral plane (i.e., within a few thousandths of an inch), even if the location of the neutral plane is shifted from a mid-plane location through the use of cavities in the smart card package, non-uniform smart card package composition, and/or the application of stickers or laminates to the smart card package. What is needed is a thinner die, such that the entire die can be situated at or near the neutral plane.
One advantage of using a thin semiconductor dice is that a smart card having enhanced RF performance is provided. For example, when an existing semiconductor dice having a thickness of 0.011 inches is used to fabricate active devices for use in a smart card, these active devices often provide electron transit times on the order of several tenths of microseconds, effectively limiting device operation to frequencies less than about 4 MHz. To this end, note that existing RF transistors for use at VHF and UHF frequencies generally use die much thinner than 0.011 inches, and typically in the range of 0.004 to 0.007 inches. By using a thin dice having a thickness in the range of from 0.004 to 0.007 inches in a smart card, relatively short electron transit times are provided, enabling active device operation in the MF, HF, VHF, UHF, and/or microwave frequency ranges.
Device operation at higher frequencies is advantageous in that a smart card is no longer limited to using industry-standard UART protocols, the fastest of which operates at 19,200 baud. (Note that other standard UART protocols used by existing smart cards operate at 2400 baud and/or 4800 baud.) In addition to being adapted for use with these conventional UART protocols, the thin smart card semiconductor die disclosed herein are also adapted for use with faster data transfer protocols and modulation schemes that operate at higher speeds than conventional UART protocols. These faster data transfer protocols and modulation schemes may be associated with higher-frequency RF carriers above 20 Khz, such as, for example, in the HV, VHF, UHF, and/or microwave regions of the RF spectrum. Such high-frequency RF carriers may be employed in conjunction with known RF modulation schemes as for example, QAM (quadrature amplitude modulation), PCM (pulse-coded modulation), FM (frequency modulation), SSB (single-sideband modulation), and others.
If a smart card uses RF encoding, as opposed to direct physical contact, for sending and receiving data, the use of a thin semiconductor dice provides another advantage. As discussed above, semiconductor die material functions as a lossy dielectric, attenuating RF signals that are incident thereupon. Since this attenuation is roughly proportional to the thickness of the die, the use of a thin die reduces the extent to which RF signals are attenuated by the smart card. This reduced attenuation, in turn, increases the maximum allowable coupling distance between a smart card and a smart card reader/writer, and also increases the number of locations in which a smart card can be held relative to a smart card reader/writer, in order to successfully read and write data from and to the smart card.
FIG. 1 is a cross-sectional view of a prior art smart card semiconductor die 101 mounted in a conventional smart card package 103. Active devices, such as transistors and diodes, are fabricated near active surface 105 of semiconductor die 101. Conventional smart card package 103 has a neutral plane which, in the cross-sectional view of FIG. 1, is represented by axis a-a′. The neutral plane is defined as the plane of substantially zero mechanical strain during mechanical flexure of the smart card package 103. The semiconductor die 101 is about 0.010 to 0.015 inches thick along axis b-b′, denoted as distance H2. The active surface 105 of the die is positioned at a distance H3 greater than 0.005 inches from the smart card neutral plane.
FIG. 2 is a cross-sectional view of a smart card semiconductor die 201 fabricated in accordance with a first embodiment disclosed herein. Typically active devices, such as transistors and diodes, are fabricated near active surface 205 of semiconductor die 201. Smart card package 203 has a neutral plane which, in the cross sectional view of FIG. 2, is represented by axis c-c′. However, unlike the semiconductor die 101 of FIG. 1, semiconductor die 201 has a thickness along axis d-d′ of about 0.004 inches, represented as H4. Axis d-d′ may be conceptualized as running parallel to the thinnest dimension of semiconductor 201, and/or running perpendicular to a plane including semiconductor die 201. The semiconductor die active surface 205 is situated at a distance H5 of 0.001 inches or less from the smart card neutral plane, represented as axis c-c′ in FIG. 2.
Although the semiconductor die 201 of FIG. 2 is very thin compared to typical 0.011-inch die, the use of a thin die is advantageous in smart card design applications. The configuration of FIG. 2 recognizes the semiconductor die 201 as a major structural, load bearing, component of the smart card. A thin die, such as semiconductor die 201, provides greater mechanical flexibility relative to a conventional die that is just barely thin enough to fit within a smart card. For example, the typical 0.011-inch die used in smart cards will not deflect as far as an 0.006-inch die if both die are fabricated to have equivalent yield strengths. The term “yield strength” is well understood by those skilled in the art.
FIG. 3 is a cross-sectional view of a thin smart card semiconductor die 301 fabricated in accordance with a second embodiment disclosed herein. As in the case of semiconductor die 201 of FIG. 2, active devices, such as transistors and diodes, are fabricated near active surface 305 of semiconductor die 301. Smart card package 303 has a neutral plane which, in the cross sectional view of FIG. 3, is represented by axis e-e′. Unlike the semiconductor die 101 of FIG. 1, semiconductor die 301 has a thickness along axis f-f′ of about 0.004 inches, represented as H8. The semiconductor die active surface 305 is situated at a distance H7 of 0.001 inches or less from the smart card neutral plane, represented as axis e-e′ in FIG. 3. Unlike the semiconductor die 201 of FIG. 2, semiconductor 301 is mounted to smart card package 303 using a physical standoff 309. Physical standoff 309 functions as a mechanical spacer, holding the active semiconductor die 301 at a desired spatial relationship with respect to the neutral axis of the smart card, denoted as e-e′. For example, this desired spatial relationship may be to position the active surface 305 of semiconductor die 301 as close as possible to the neutral axis of the smart card. An optional bonding agent may be employed to fasten the physical standoff to the semiconductor die and/or to the smart card package 303. Virtually any material can be employed for the bonding agent, so long as the material adheres to semiconductor die 301, and/or to smart card package 303. However, the elastic properties of the bonding agent should also be considered. For example, the bonding agent should be relatively elastic, deformable, and flexible, to provide the semiconductor die 301 with some freedom of motion relative to the smart card package while the smart card package is being bent. Rubber, epoxies, cyanoacrylate esters (acrylics), and/or other types of materials are suitable for use as bonding agents.
FIG. 4 is a table comparing various physical parameters of the smart card semiconductor die shown in FIGS. 1, 2, and 3. The design of FIG. 1 has a die thickness of 0.015 inches, and the active surface of the semiconductor die is positioned at a relatively great distance of about 0.006 inches from the neutral plane of the smart card. When this smart card is bent, the active surface of the semiconductor die will experience relatively great forces due to the relatively great distance between the neutral plane and the active surface. By contrast, the smart card design of FIG. 2 has a die thickness of 0.006 inches, and the active surface of the semiconductor die is positioned at a relatively short distance of 0.0005 inches from the neutral plane of the smart card. When this smart card is bent, the active surface of the semiconductor die will experience relatively minimal forces due to the relatively short distance between the neutral plane and the active surface. Similarly, the smart card structure of FIG. 3 has a die thickness of 0.004 inches and the active surface of the semiconductor die is situated 0.002 inches from the neutral plane of the smart card.
FIG. 5 is a cross-sectional view of a smart card 500 constructed in accordance with FIG. 3 and in a state of mechanical flexure. Such mechanical flexure exists, for example, when a user bends the smart card 500. One must assume that smart cards will be exposed to flexure during conditions of ordinary or typical usage. The smart card 500 shown in FIG. 5 has a thickness H9, an upper surface 502, a lower surface 504, a left-hand edge 506, and a right-hand edge 508. The smart card is flexed (bent), thus forming an arcuate surface at a radius 593 from a focal point 591. In other words, the edges 506, 508 of the smart card are being forced together, and the middle of the smart card along axis f-f′ is being pushed upwards. This may happen if the smart card 500 is resting on a surface, and someone grasps the card at opposite ends with thumb and fingertips while moving thumb and fingertips closer together, or when smart card 500 is placed in a wallet in the smart card user's rear pocket and the user proceeds to assume a sitting position. A region of tensile stress 522 is formed above the neutral plane, represented by axis e-e′ in FIG. 5, and a region of compressive stress 524 is formed below axis e-e′. A semiconductor die 301 is incorporated into smart card 500, and this die has a thickness of H9. The strains within smart card 500 are shown as vectors 520.
A plan view of the smart card 500 described in FIG. 5 is illustrated in FIG. 6. Referring now to FIG. 6, a smart card 500 is shown, along with representative locations for various smart card components. For example, smart card 500 includes microprocessor 302, chip capacitors 304, and a voltage regulation/data conditioning die 306.
A more detailed cross-sectional view of the smart card 500 of FIG. 5 is shown in FIG. 7. In the example of FIG. 7, semiconductor die 301 is a thin semiconductor die having a thickness less than 0.011 inches and positioned at or near the neutral plane of the smart card package 303. The smart card 500 includes one or more polyvinyl chloride (PVC) labels 402, 403 which are affixed to upper and lower surfaces, respectively, of smart card 500 with adhesive layers 404, 405, respectively. Adhesive layer 404 adjoins woven material 408. Woven material 408 is affixed to polyester structural members 410 using an adhesive layer 412. Polyester structural members 410 and adhesive layers 412 are configured to form a cavity, in which is mounted semiconductor die 301. Die attach epoxy 417 and optional mechanical stand-off material is used to mount the semiconductor die 301 onto a copper pad 419. Die encapsulation material 427 is used to protect and insulate the semiconductor die 301, and to maintain the spacing and positioning of wire bonds 423. Die encapsulation material 427 should have very high resistivity, i.e. be a good electrical insulator, provide good thermal conductivity to carry heat away from semiconductor die 301, provide a hermetic and watertight seal, adhere well to semiconductor die 301, provide mechanical flexibility and deformability, and provide non-corrosivity with respect to the semiconductor die 301 and any metallic traces that are connected to semiconductor die 301. Copper pad 419 is traced onto a polyester printed circuit board 426, which may include additional copper pads 421. All or some of these additional copper pads 421 may be electrically connected to the semiconductor die 301 via one or more wire bonds 423. Adhesive layer 405 is used to attach PVC label 403 to the underside of the printed circuit board 426.
When the smart card 500 is bent, the resulting mechanical strains are shown as vectors 520 in FIG. 5. At a given distance from the neutral plane of the smart card, these strains are lowest in relatively stiff smart card structural components and greatest in relatively flexible smart card structural components. With respect to FIG. 7, strains are lowest in structural components such as semiconductor die 301, and strains are greater in polyester structural members 410 and adhesive layers 404 and 405. However, the magnitude of mechanical strain existing in a given smart card component is also dependent upon the positioning of that component relative to the neutral plane of the smart card. In general, the strains for each component are greatest near the outer surface of the component and at a maximum near polyvinyl chloride (PVC) labels 402 and 403. The strains are zero along axis e-e′, representing a two-dimensional projection of the neutral plane in FIG. 7. If the smart card 500 of FIG. 7 is bent as shown in FIG. 5, then the smart card structural components above this neutral plane are in tension, and the structural components below this neutral plane are in compression. The semiconductor die 301 is positioned so that the devices (diodes and transistors) on the die are at or near (within 0.007 inches of) the neutral plane.
In order to mathematically calculate the amount of strain on semiconductor die 301 when this die is packaged into a smart card 500, and to calculate the location of the neutral plane within the smart card 500, the entire smart card structure of FIG. 7 must be considered. This calculation requires the performance of mathematically complex operations that are best completed using an analysis tool known to those skilled in the art as the finite element method. However, to simplify matters a bit, in practice, the loading on the chip is determined by card flexure and is dominated by the shape of the card structure. To simplify further, when the chip cavity of FIG. 7 is omitted from the calculation of mechanical strain, the neutral plane, represented by axis e-e′, is at a distance H10 from the upper smart card surface, and also at a distance of H10 from the lower smart card surface. In other words, the neutral plane is situated halfway between the upper and lower smart card surfaces, i.e., in the mid-plane of the smart card 500.
Reducing H10 reduces the amount of stress on the smart card die 301. This reduction in H10 is achieved by using as thin a die as is practicable for semiconductor die 301. Further improvements are achieved by constructing smart card 500 such that the most fragile portion of the semiconductor die 301 is at or near the neutral plane. This portion is typically the location at which active devices, such as transistors and diodes, are situated within the semiconductor die 301. More specifically, the interface between the conducting (metal-doped) portion of the die and the semiconducting (i.e., N- or P-doped silicon body) of the remainder of the die is the most fragile portion of semiconductor die 301. This interface is approximated by the active surface defined above. Locating this interface at the neutral plane further protects the semiconductor die 301 from mechanical strain, resulting in a smart card 500 with improved reliability. polyvinyl chloride (PVC) labels 402 and 403. The strains are
Traditional smart card packaging techniques place the die near the surface of the card due to stringent packaging and interconnect requirements. However, according to an embodiment disclosed herein, semiconductor die 301 are situated as close as possible to the neutral plane, e-e′, of smart card 500. In this manner, the effective level of mechanical stress transmitted to the semiconductor die 301 by the smart card package 303 during mechanical flexure is substantially reduced. The smart card package 303 thus affords extra protection to the semiconductor die 301 by reducing the mechanical stresses realized upon the die.
Various techniques may be employed to fabricate the relatively thin semiconductor die 201 (FIG. 2) and 301 (FIGS. 3, 5, and 7) of the embodiments disclosed herein. However, note that traditional semiconductor die fabrication techniques for conventional 0.011-inch die cannot be used to effectively fabricate thin die having a thickness of 0.008 inches or less. These existing techniques are designed to maximize the number of usable 0.011-inch semiconductor die produced during a given time period. If the die are handled and produced too carefully, it will take too long to produce the die, and production efficiency will suffer. On the other hand, if the die are handled and produced too roughly, more die will be produced, but an undesirable high proportion of these die will be defective and unusable. Therefore, existing techniques strike a balance between rough handling and careful handling, so that the maximum number of usable 0.011-inch die will be generated during a given time interval.
When these existing techniques are applied to fabricate thin die of 0.008 inches or less, the thinner die are more fragile during the handling and fabrication process than conventional 0.011-inch smart card semiconductor die. Substantially improved yields of thin semiconductor die may be obtained if special die fabrication techniques are applied to the semiconductor wafer from which the thin semiconductor die are made. These fabrication techniques include taping the semiconductor wafer with conventional UV dicing tape and then immersing the wafer into an acid bath. The acid bath, which may include nitric acid, hydrofluoric acid, and acetic acid in relative proportions of 7:2:1, provides chemical stress relief for the semiconductor wafer. Additionally, the semiconductor wafer may be diced using a dicing saw, soft rubber or plastic die pickup heads, non-piercing ejector pins, and servo or programmable dynamic ejector pins to reduce or eliminate die damage. Moreover, the die may be ejected from the dicing tape using velocity-controlled or programmable servo-controlled, non-piercing ejector pins. Suitable techniques for manufacturing smart card semiconductor die are set forth in greater detail in U.S. Pat. No. 5,480,842 entitled, “Method for Fabricating Thin, Strong and Flexible Die for Smart Cards”.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4962415||Feb 6, 1990||Oct 9, 1990||Hitachi Maxell, Ltd.||IC card|
|US5163728 *||Nov 15, 1990||Nov 17, 1992||Miller Charles F||Tweezer semiconductor die attach method and apparatus|
|US5480842 *||Apr 11, 1994||Jan 2, 1996||At&T Corp.||Method for fabricating thin, strong, and flexible die for smart cards|
|US5489637 *||Feb 22, 1995||Feb 6, 1996||Johnson Matthey Inc||Low temperature flexible die attach adhesive and articles using same|
|US5546275 *||Jun 14, 1995||Aug 13, 1996||Motorola, Inc.||Electrical module mounting apparatus|
|US5561328 *||Apr 14, 1995||Oct 1, 1996||Digital Equipment Corporation||Photo-definable template for semiconductor chip alignment|
|US5619165 *||Apr 6, 1995||Apr 8, 1997||Sgs-Thomson Microelectronics, S.A.||Voltage threshold detection circuit with very low consumption|
|US5719437 *||Apr 19, 1996||Feb 17, 1998||Lucent Technologies Inc.||Smart cards having thin die|
|US6051877 *||Jul 3, 1997||Apr 18, 2000||Hitachi, Ltd.||Semiconductor device and fabrication method|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7193239 *||Jul 3, 2003||Mar 20, 2007||Elm Technology Corporation||Three dimensional structure integrated circuit|
|US7344087 *||Oct 20, 2004||Mar 18, 2008||Samsung Electronics Co., Ltd.||IC card, IC card processor and IC card system to improve data transmission speed|
|US7385280 *||Oct 21, 2005||Jun 10, 2008||Seiko Epson Corporation||Electronic device package and electronic equipment|
|US7670893||Nov 3, 2003||Mar 2, 2010||Taiwan Semiconductor Manufacturing Co., Ltd.||Membrane IC fabrication|
|US7705466||Sep 26, 2003||Apr 27, 2010||Elm Technology Corporation||Three dimensional multi layer memory and control logic integrated circuit structure|
|US7763948||Jul 27, 2010||Taiwan Semiconductor Manufacturing Co., Ltd.||Flexible and elastic dielectric integrated circuit|
|US7786562||Jun 10, 2005||Aug 31, 2010||Volkan Ozguz||Stackable semiconductor chip layer comprising prefabricated trench interconnect vias|
|US7820469||Jun 11, 2003||Oct 26, 2010||Taiwan Semiconductor Manufacturing Co., Ltd.||Stress-controlled dielectric integrated circuit|
|US7911012||Mar 22, 2011||Taiwan Semiconductor Manufacturing Co., Ltd.||Flexible and elastic dielectric integrated circuit|
|US8035233||Oct 11, 2011||Elm Technology Corporation||Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer|
|US8080442||Jun 21, 2008||Dec 20, 2011||Elm Technology Corporation||Vertical system integration|
|US8168470 *||May 1, 2012||Stats Chippac, Ltd.||Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound|
|US8269327||Jun 21, 2008||Sep 18, 2012||Glenn J Leedy||Vertical system integration|
|US8288206||Jul 4, 2009||Oct 16, 2012||Elm Technology Corp||Three dimensional structure memory|
|US8318538||Mar 17, 2009||Nov 27, 2012||Elm Technology Corp.||Three dimensional structure memory|
|US8410617||Apr 2, 2013||Elm Technology||Three dimensional structure memory|
|US8587102||May 9, 2008||Nov 19, 2013||Glenn J Leedy||Vertical system integration|
|US8629542||Mar 17, 2009||Jan 14, 2014||Glenn J. Leedy||Three dimensional structure memory|
|US8791581||Oct 23, 2013||Jul 29, 2014||Glenn J Leedy||Three dimensional structure memory|
|US8796862||Aug 9, 2013||Aug 5, 2014||Glenn J Leedy||Three dimensional memory structure|
|US8824159||Mar 31, 2009||Sep 2, 2014||Glenn J. Leedy||Three dimensional structure memory|
|US8841778||Aug 9, 2013||Sep 23, 2014||Glenn J Leedy||Three dimensional memory structure|
|US8907499||Jan 4, 2013||Dec 9, 2014||Glenn J Leedy||Three dimensional structure memory|
|US8928119||Mar 17, 2009||Jan 6, 2015||Glenn J. Leedy||Three dimensional structure memory|
|US8933570||Mar 17, 2009||Jan 13, 2015||Elm Technology Corp.||Three dimensional structure memory|
|US9087556||Aug 12, 2014||Jul 21, 2015||Glenn J Leedy||Three dimension structure memory|
|US20020132465 *||May 13, 2002||Sep 19, 2002||Elm Technology Corporation||Reconfigurable integrated circuit memory|
|US20020180605 *||Jul 16, 2002||Dec 5, 2002||Ozguz Volkan H.||Wearable biomonitor with flexible thinned integrated circuit|
|US20030057564 *||Aug 19, 2002||Mar 27, 2003||Elm Technology Corporation||Three dimensional structure memory|
|US20030173608 *||Mar 3, 2003||Sep 18, 2003||Elm Technology Corporation||Three dimensional structure integrated circuit|
|US20030218182 *||Jun 11, 2003||Nov 27, 2003||Leedy Glenn J.||Strees-controlled dielectric integrated circuit|
|US20030223535 *||Mar 7, 2003||Dec 4, 2003||Leedy Glenn Joseph||Lithography device for semiconductor circuit pattern generator|
|US20040070063 *||Sep 26, 2003||Apr 15, 2004||Elm Technology Corporation||Three dimensional structure integrated circuit|
|US20040097008 *||Jul 3, 2003||May 20, 2004||Elm Technology Corporation||Three dimensional structure integrated circuit|
|US20040132231 *||Dec 18, 2003||Jul 8, 2004||Elm Technology Corporation.||Lithography device for semiconductor circuit pattern generator|
|US20040150068 *||Dec 19, 2003||Aug 5, 2004||Elm Technology Corporation||Membrane 3D IC fabrication|
|US20040151043 *||Dec 18, 2003||Aug 5, 2004||Elm Technology Corporation||Three dimensional structure memory|
|US20040192045 *||Jan 27, 2004||Sep 30, 2004||Elm Technology Corporation.||Apparatus and methods for maskless pattern generation|
|US20040197951 *||Nov 3, 2003||Oct 7, 2004||Leedy Glenn Joseph||Membrane IC fabrication|
|US20050051841 *||Jun 11, 2003||Mar 10, 2005||Leedy Glenn Joseph||Stress-controlled dielectric integrated circuit|
|US20050082626 *||Dec 18, 2003||Apr 21, 2005||Elm Technology Corporation||Membrane 3D IC fabrication|
|US20050082641 *||Oct 22, 2004||Apr 21, 2005||Elm Technology Corporation||Flexible and elastic dielectric integrated circuit|
|US20050092847 *||Oct 20, 2004||May 5, 2005||Samsung Electronics Co., Ltd.||IC card, IC card processor and IC card system to improve data transmission speed|
|US20050130351 *||Jan 27, 2004||Jun 16, 2005||Elm Technology Corporation||Methods for maskless lithography|
|US20050156265 *||Jan 24, 2005||Jul 21, 2005||Elm Technology Corporation||Lithography device for semiconductor circuit pattern generation|
|US20050176174 *||Sep 19, 2003||Aug 11, 2005||Elm Technology Corporation||Methodof making an integrated circuit|
|US20050277288 *||Jun 10, 2005||Dec 15, 2005||Volkan Ozguz||Stackable semiconductor chip layer comprising prefabricated trench interconnect vias|
|US20060097373 *||Oct 21, 2005||May 11, 2006||Wataru Ito||Electronic device package and electronic equipment|
|US20080251941 *||Jun 21, 2008||Oct 16, 2008||Elm Technology Corporation||Vertical system integration|
|US20080254572 *||Jun 21, 2008||Oct 16, 2008||Elm Technology Corporation||Vertical system integration|
|US20080302559 *||Jan 18, 2008||Dec 11, 2008||Elm Technology Corporation||Flexible and elastic dielectric integrated circuit|
|US20090219744 *||Mar 17, 2009||Sep 3, 2009||Leedy Glenn J||Three dimensional structure memory|
|US20100140772 *||Dec 8, 2008||Jun 10, 2010||Stats Chippac, Ltd.||Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound|
|US20100173453 *||Jul 8, 2010||Leedy Glenn J||Three dimensional structure memory|
|US20100291735 *||Nov 18, 2010||Volkan Ozguz||Stackable semiconductor chip layer comprising prefabricated trench interconnect vias|
|U.S. Classification||257/679, 257/669, 257/728, 257/782|
|International Classification||H01L23/04, H01L23/08, G06K19/077|
|Cooperative Classification||G06K19/07728, G06K19/07745, H01L2924/0002|
|European Classification||G06K19/077E5, G06K19/077M|
|Jul 20, 2005||FPAY||Fee payment|
Year of fee payment: 8
|Aug 13, 2009||FPAY||Fee payment|
Year of fee payment: 12
|Mar 7, 2013||AS||Assignment|
Free format text: SECURITY INTEREST;ASSIGNOR:ALCATEL-LUCENT USA INC.;REEL/FRAME:030510/0627
Owner name: CREDIT SUISSE AG, NEW YORK
Effective date: 20130130
|Oct 9, 2014||AS||Assignment|
Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG;REEL/FRAME:033950/0001
Effective date: 20140819
Owner name: ALCATEL-LUCENT USA INC., NEW JERSEY