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Publication numberUSRE37751 E1
Publication typeGrant
Application numberUS 09/695,035
Publication dateJun 18, 2002
Filing dateOct 25, 2000
Priority dateApr 28, 1997
Fee statusPaid
Publication number09695035, 695035, US RE37751 E1, US RE37751E1, US-E1-RE37751, USRE37751 E1, USRE37751E1
InventorsPantas Sutardja
Original AssigneeMarvell International Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Apparatus and method for transient suppression in synchronous data detection systems
US RE37751 E1
Abstract
Disclosed is a method for transient suppression in synchronous data protection systems which includes high-pass filtering of the signal produced by the sampling and shaping circuits before the signal enters the timing and gain control circuits. This high-pass filtering may be turned on when a transient is detected, in anticipation of a previously detected transient, or may be always on. Using the high-pass version of the shaped signal allows the timing loop and the gain loop to function during a transient interval, thus maintaining timing and gain lock during such an interval.
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Claims(72)
What is claimed is:
1. An apparatus for suppression of transients in a synchronous data detection system comprising:
an analog front-end circuit receiving an analog signal and outputting an amplified signal;
a sampler receiving the amplified signal and outputting a sampled signal;
a shaping circuit receiving the sampled signal and outputting a shaped signal;
a data detector receiving the shaped signal and detecting data in the shaped signal;
a first high-pass filter receiving the shaped signal and outputting a high-pass signal;
a gain control circuit receiving the high-pass signal and controlling the analog front-end circuit using the high-pass signal; and
a timing control circuit receiving the high-pass signal and controlling the sampler and the shaping circuit using the high-pass signal.
2. The apparatus in claim 1, wherein the first high-pass filter is bypassable.
3. The apparatus in claim 2, further comprising An apparatus for suppression of transients in a synchronous data detection system comprising:
an analog front-end circuit receiving an analog signal and outputting an amplified signal;
a sampler receiving the amplified signal and outputting a sampled signal;
a shaping circuit receiving the sampled signal and outputting a shaped signal;
a data detector receiving the shaped signal and detecting data in the shaped signal;
a first high-pass filter receiving the shaped signal and outputting a high-pass signal, wherein the first high-pass filter is bypassable;
a gain control circuit receiving the high-pass signal and controlling the analog front-end circuit using the high-pass signal;
a timing control circuit receiving the high-pass signal and controlling the sampler and the shaping circuit using the high-pass signal; and
a transient detector receiving the sampled signal and using the sampled signal to control bypassing of the first high-pass filter.
4. The apparatus in claim 3, wherein the first high-pass filter is switched on when a transient is detected by the transient detector.
5. The apparatus in claim 3, wherein the first high-pass filter is switched on in anticipation of a transient that was previously detected by the transient detector.
6. The apparatus in claim 1, wherein the analog front-end circuit comprises a variable gain amplifier (VGA).
7. The apparatus in claim 6, wherein the analog front-end further comprises a second high-pass filter.
8. The apparatus in claim 7, wherein the second high-pass filter is bypassable.
9. The apparatus in claim 1, wherein the sampler comprises an analog-to-digital converter.
10. The apparatus in claim 1, wherein the sampler comprises a sample-and-hold circuit.
11. The apparatus in claim 1, wherein the shaping circuit comprises a finite impulse response (FIR) filter.
12. The apparatus in claim 1, wherein the data detector comprises a maximum-likelihood sequence detector.
13. The apparatus in claim 1, further comprising a voltage controlled oscillator (VCO) receiving a voltage input from the timing control circuit and outputting an oscillating signal to the sampler and the shaping circuit.
14. A method for robust data detection in a synchronous data detection system comprising:
receiving a signal including a transient in a baseline of the signal;
amplifying the signal under control of a gain control signal to form an amplified signal;
sampling the amplified signal under control of a timing control signal to form a sampled signal;
shaping the sampled signal under control of the timing control signal to form a shaped signal;
recovering data from the shaped signal;
high-pass filtering the shaped signal to form a high-pass version of the shaped signal;
generating the gain control signal using the high-pass version of the shaped signal; and
generating the timing control signal using the high-pass version of the shaped signal.
15. An apparatus for suppression of transients in a synchronous data detection system comprising:
an analog front-end circuit receiving an analog signal and outputting an amplified signal;
a sampler receiving the amplified signal and outputting a sampled signal;
a data detector responsive to the sampled signal to detect data therein;
a first high-pass filter responsive to the sampled signal and outputting a high-pass signal;
a gain control circuit receiving the high-pass signal and controlling the analog front-end circuit using the high-pass signal; and
a timing control circuit receiving the high-pass signal and controlling the sampler in accordance with the high-pass signal.
16. The apparatus in claim 15, wherein the first high-pass filter is bypassable.
17. The apparatus in claim 15, wherein the analog front-end circuit comprises a variable gain amplifier (VGA).
18. The apparatus in claim 17, wherein the analog front-end further comprises a second high-pass filter.
19. The apparatus in claim 18, wherein the second high-pass filter is bypassable.
20. The apparatus in claim 15, wherein the sampler comprises an analog-to-digital converter.
21. The apparatus in claim 15, wherein the sampler comprises a sample-and-hold circuit.
22. The apparatus in claim 15, wherein the data detector comprises a maximum-likelihood sequence detector.
23. The apparatus in claim 15, further comprising a voltage controlled oscillator (VCO) receiving a voltage input from the timing control circuit and outputting an oscillating signal to the sampler.
24. An apparatus for suppression of transients in a synchronous data detection system comprising:
an analog front-end circuit receiving an analog signal and outputting an amplified signal;
a sampler receiving the amplified signal and outputting a sampled signal;
a data detector responsive to the sampled signal to detect data therein;
a first high-pass filter responsive to the sampled signal and outputting a high-pass signal, wherein the first high-pass filter is bypassable;
a gain control circuit receiving the high-pass signal and controlling the analog front-end circuit using the high-pass signal;
a timing control circuit receiving the high-pass signal and controlling the sampler in accordance with the high-pass signal; and
a transient detector responsive to the sampled signal to control bypassing of the first high-pass filter.
25. The apparatus in claim 24, wherein the first high-pass filter is switched on when a transient is detected by the transient detector.
26. The apparatus in claim 24, wherein the transient detector controls said analog front end circuit.
27. The apparatus in claim 24, wherein the first high-pass filter is switched on in anticipation of a transient that was previously detected by the transient detector.
28. A method for data detection in a synchronous data detection system comprising:
a. receiving a signal including a transient component;
b. amplifying the signal under control of a gain control signal to form an amplified signal;
c. sampling the amplified signal under control of a timing control signal to form a sampled signal;
d. recovering data from the sampled signal;
e. high-pass filtering the sampled signal to form a high-pass version of the sampled signal;
f. generating the gain control signal using the high-pass version of the sampled signal; and
g. generating the timing control signal using the high-pass version of the sampled signal.
29. The method of claim 28 further comprising the step of:
ff. high-pass filtering the amplified signal.
30. The method of claim 29, further comprising the step of:
gg. bypassing step ff.
31. A method for data detection in a synchronous data detection system comprising:
a. receiving a signal including a transient component;
b. amplifying the signal under control of a gain control signal to form an amplified signal;
c. sampling the amplified signal under control of a timing control signal to form a sampled signal;
d. recovering data from the sampled signal;
e. high-pass filtering the sampled signal to form a high-pass version of the sampled signal;
f. generating the gain control signal using the high-pass version of the sampled signal;
g. generating the timing control signal using the high-pass version of the sampled signal; and
h. detecting a transient in step c; and
i. bypassing step e in response to step h.
32. The method of claim 31, wherein step i further comprises bypassing step e when a transient is detected in step h.
33. The method of claim 32, wherein step i further comprises bypassing step e when a transient is anticipated that was previously detected in step h.
34. An apparatus for suppression of transients in a synchronous data detection system comprising:
an analog front-end circuit receiving an analog signal and outputting an amplified signal;
a sampler receiving the amplified signal and outputting a sampled signal;
a shaping circuit receiving the sampled signal and outputting a shaped signal;
a data detector receiving the shaped signal to detecting data therein;
a first high-pass filter receiving the shaped signal and outputting a high-pass signal; and
a timing control circuit receiving the high-pass signal and controlling the sampler and the shaping circuit using the high-pass signal.
35. The apparatus in claim 34, wherein the first high-pass filter is bypassable.
36. The apparatus in claim 34, wherein the analog front-end circuit comprises a variable gain amplifier (VGA).
37. The apparatus in claim 36, wherein the analog front-end further comprises a second high-pass filter.
38. The apparatus in claim 37, wherein the second high-pass filter is bypassable.
39. The apparatus in claim 34, wherein the sampler comprises an analog-to-digital converter.
40. The apparatus in claim 34, wherein the sampler comprises a sample-and-hold circuit.
41. The apparatus in claim 34, wherein the data detector comprises a maximum-likelihood sequence detector.
42. The apparatus in claim 34, further comprising a voltage controlled oscillator (VCO) receiving a voltage input from the timing control circuit and outputting an oscillating signal to the sampler.
43. The apparatus in claim 34, wherein the shaping circuit comprises a finite impulse response (FIR) filter.
44. An apparatus for suppression of transients in a synchronous data detection system comprising:
an analog front-end circuit receiving an analog signal and outputting an amplified signal;
a sampler receiving the amplified signal and outputting a sampled signal;
a shaping circuit receiving the sampled signal and outputting a shaped signal;
a data detector receiving the shaped signal to detecting data therein;
a first high-pass filter receiving the shaped signal and outputting a high-pass signal, wherein the first high-pass filter is bypassable;
a timing control circuit receiving the high-pass signal and controlling the sampler and the shaping circuit using the high-pass signal; and
a transient detector responsive to the sampled signal to control bypassing of the first high-pass filter.
45. The apparatus in claim 44, wherein the first high-pass filter is switched on when a transient is detected by the transient detector.
46. The apparatus in claim 44, wherein the transient detector controls said analog front end circuit.
47. The apparatus in claim 44, wherein the first high-pass filter is switched on in anticipation of a transient that was previously detected by the transient detector.
48. A method for data detection in a synchronous data detection system comprising:
a. receiving a signal including a transient component;
b. amplifying the signal under control of a gain control signal to form an amplified signal;
c. sampling the amplified signal under control of a timing control signal to form a sampled signal;
d. shaping the sampled signal under control of the timing control signal to form a shaped signal;
e. recovering data from the shaped signal;
f. high-pass filtering the shaped signal to form a high-pass version of the shaped signal; and
g. generating the timing control signal using the high-pass version of the shaped signal.
49. The method of claim 48, further comprising the step of:
yy. high-pass filtering the amplified signal.
50. The method of claim 49, further comprising the step of:
zz. bypassing step yy.
51. A method for data detection in a synchronous data detection system comprising:
a. receiving a signal including a transient component;
b. amplifying the signal under control of a gain control signal to form an amplified signal;
c. sampling the amplified signal under control of a timing control signal to form a sampled signal;
d. shaping the sampled signal under control of the timing control signal to form a shaped signal;
e. recovering data from the shaped signal;
f. high-pass filtering the shaped signal to form a high-pass version of the shaped signal;
g. generating the timing control signal using the high-pass version of the shaped signal;
h. detecting a transient in step c; and
i. bypassing step f in response to step h.
52. The method of claim 51, wherein step i further comprises bypassing step e when a transient is detected in step h.
53. The method of claim 51, wherein step i further comprises bypassing step e when a transient is anticipated that was previously detected in step h.
54. An apparatus for suppression of transients in a synchronous data detection system comprising:
an analog front-end circuit receiving an analog signal and outputting an amplified signal;
a sampler receiving the amplified signal and outputting a sampled signal;
a shaping circuit receiving the sampled signal and outputting a shaped signal;
a data detector receiving the shaped signal and detecting data in the shaped signal;
a first high-pass filter receiving the shaped signal and outputting a high-pass signal; and
a gain control circuit receiving the high-pass signal and controlling the analog front-end circuit using the high-pass signal.
55. The apparatus in claim 54, wherein the first high-pass filter is bypassable.
56. The apparatus in claim 54, wherein the analog front-end circuit comprises a variable gain amplifier (VGA).
57. The apparatus in claim 56, wherein the analog front-end further comprises a second high-pass filter.
58. The apparatus in claim 57, wherein the second high-pass filter is bypassable.
59. The apparatus in claim 54, wherein the sampler comprises an analog-to-digital converter.
60. The apparatus in claim 54, wherein the sampler comprises a sample-and-hold circuit.
61. The apparatus in claim 54, wherein the data detector comprises a maximum-likelihood sequence detector.
62. The apparatus in claim 54, wherein the shaping circuit comprises a finite impulse response (FIR) filter.
63. An apparatus for suppression of transients in a synchronous data detection system comprising:
an analog front-end circuit receiving an analog signal and outputting an amplified signal;
a sampler receiving the amplified signal and outputting a sampled signal;
a shaping circuit receiving the sampled signal and outputting a shaped signal;
a data detector receiving the shaped signal and detecting data in the shaped signal;
a first high-pass filter receiving the shaped signal and outputting a high-pass signal, wherein the first high-pass filter is bypassable;
a gain control circuit receiving the high-pass signal and controlling the analog front-end circuit using the high-pass signal; and
a transient detector responsive to the sampled signal to control bypassing of the first high-pass filter.
64. The apparatus in claim 63, wherein the first high-pass filter is switched on when a transient is detected by the transient detector.
65. The apparatus in claim 63, wherein the first high-pass filter is switched on in anticipation of a transient that was previously detected by the transient detector.
66. The apparatus in claim 63, wherein the transient detector controls said analog front end circuit.
67. A method for data detection in a synchronous data detection system comprising:
a. receiving a signal including a transient component;
b. amplifying the signal under control of a gain control signal to form an amplified signal;
c. sampling the amplified signal under control of a timing control signal to form a sampled signal;
d. shaping the sampled signal under control of the timing control signal to form a shaped signal;
e. recovering data from the shaped signal;
f. high-pass filtering the shaped signal to form a high-pass version of the shaped signal; and
g. generating the gain control signal using the high-pass version of the shaped signal.
68. The method of claim 67, further comprising the step of:
j. high-pass filtering the amplified signal.
69. The method of claim 68, further comprising the step of:
k. bypassing step j.
70. A method for data detection in a synchronous data detection system comprising:
a. receiving a signal including a transient component;
b. amplifying the signal under control of a gain control signal to form an amplified signal;
c. sampling the amplified signal under control of a timing control signal to form a sampled signal;
d. shaping the sampled signal under control of the timing control signal to form a shaped signal;
e. recovering data from the shaped signal;
f. high-pass filtering the shaped signal to form a high-pass version of the shaped signal;
g. generating the gain control signal using the high-pass version of the shaped signal;
h. detecting a transient in step c; and
i. bypassing step f in response to step h.
71. The method of claim 70, wherein step i further comprises bypassing step e when a transient is detected in step h.
72. The method of claim 70, wherein step i further comprises bypassing step e when a transient is anticipated that was previously detected in step h.
Description
BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates to transient suppression techniques in synchronous data detection systems. These techniques are applicable for robust gain control, timing, and data recovery in a read channel of a magnetic recording system.

2. Description of Related Art

The magnetic storage industry has been increasing the areal density storage capacity of hard drives with various technological advancements to meet the computer industry's demand for more and better storage. Such advancements include the use of magnetoresistive (MR) heads and partial-response maximum likelihood (PRML) sequence detection. A MR head includes a MR element made out of a material which changes electrical resistance depending on the strength of the magnetic field in which it lies. A PRML system is a synchronous data detection system which includes partial-response signalling and maximum likelihood sequence detection.

MR heads are known in the industry to suffer from a transient phenomenon commonly referred to as thermal asperity (TA) events. A MR head normally glides over a spinning magnetic disk close to, but not touching, the disk surface. When a MR head hits a protruding object on the disk surface, the MR element heats up rapidly and the heat decays relatively slowly.

The effect of such a transient phenomenon is a sudden transient change in the baseline of the read-back signal coming from the MR head. This transient change contains a substantial low frequency component and causes loss of read-back data.

The extent of the read-back data lost due to such a transient depends on the robustness of the data detection system. A data detection system without any transient detection and suppression circuit may lose a large amount of data, even to the point that the error correcting code (ECC) used in the recording system cannot regenerate the user data.

A prior art method of handling a transient includes the following steps. First, the system detects the transient and halts data detection. Second, an analog front-end portion of the system is switched to high-pass mode to reduce the effect of the transient. Third, the system freezes both the gain of the gain control loop and the timing of the timing recovery loop. Fourth, the system waits for a period of time until the effect of the transient is below some threshold. This period of time is called the transient interval. Fifth, when the transient interval is over, the system resumes data detection. Sixth, the front-end is switched back to a lower AC coupling and the gain and timing are unfrozen.

There are at least two problems with the prior art method. First, even with the front-end high-pass function switched on, the transient interval is still quite long. Such a long transient interval may result in a loss of read-back data beyond the point of recovery by the ECC. Second, freezing the timing recovery and gain control loops means that the system halts tracking the timing and gain variations in the read-back signal. If the channel timing is not fully settled when the system is hit with a TA event, then freezing the timing loop will cause a large drift in the synchronous sampling points which may result in permanent synchronization loss and complete loss of user data. This problem has been shown both experimentally and through modelling.

SUMMARY

The present invention relates to a system and method for transient suppression in a synchronous data detection system. The present invention includes high-pass filtering of the signal produced by the sampling and shaping circuits before the signal enters the timing and gain control circuits. This high-pass filtering may be turned on when a transient is detected, in anticipation of a previously detected transient, or may be always on. Using the high-pass version of the shaped signal allows the timing loop and the gain loop to function during a transient interval, thus maintaining timing and gain lock during such an interval.

This high-pass filtering of the signal entering the timing and gain control circuits facilitates the tracking of the timing and gain variations in the read-back signal. The resulting improvements in tracking capability reduces the necessary length of the transient interval which shortens the time period during which tracking is halted. A shorter time during which tracking is halted leads to less read-back data loss and smaller drift in the synchronous sampling points. Thus, loss of read-back data beyond the point of recovery by ECC and permanent synchronization loss are prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other more detailed and specific objects and features of the present invention are more fully disclosed in the following specification, reference being had to the accompanying drawings, in which:

FIG. 1A is a diagram of a first prior art synchronous data detection system.

FIG. 1B is a diagram of a first analog front-end circuit for the first prior art synchronous data detection system.

FIG. 1C is a diagram of a second analog front-end circuit, including a high-pass filter, for the first prior art synchronous data detection system.

FIG. 1D is a diagram of a high-pass filter.

FIG. 2A is a diagram of a second prior art synchronous detection system, including a transient detector.

FIG. 2B is a diagram of an analog front-end circuit, including a bypassable high-pass filter, for the second prior art synchronous detection system.

FIG. 2C is a diagram of a bypassable high-pass filter.

FIG. 2D is a diagram of a transient detector.

FIG. 2E shows illustrative graphs of various signals in the transient detector.

FIG. 3A is a diagram of a third synchronous data detection system, including a high-pass filter, in a first and alternate embodiment of the present invention.

FIG. 3B shows illustrative graphs of the input and output of the high-pass filter in the third synchronous data detection system.

FIG. 4 is a diagram of a fourth synchronous data detection system, including a bypassable high-pass filter, in a second and preferred embodiment of the present invention.

FIG. 5 is a diagram of a fifth synchronous data detection system in a third and alternate embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1A is a diagram of a first prior art synchronous data detection system 100. Analog Front-End portion 102 or 103 receives an analog signal. In a typical magnetic storage system, this signal comes from the magnetic head. A constant signal level is desirable. Therefore, the analog front-end 102 or 103 typically contains a variable gain amplifier (VGA) 120 circuit. To keep the signal level constant, the VGA 120 receives a control signal from the gain control circuit 114. The analog front-end 102 or 103 outputs an amplified signal.

Sampler circuit 104 receives the amplified signal from the analog front-end 102 or 103. The sampler 104 may be an Analog-to-Digital Converter (ADC). The sampling is controlled by a clock signal output by a voltage controlled oscillator (VCO) 112. The frequency and phase of the clock signal output by the VCO 112 is controlled by a timing control circuit 110. If the sampler 104 is an ADC, the sampler 104 outputs a stream of digital samples. The sampler 104 may also be a sample-and-hold (SH) circuit. If the sampler 104 is a SH, it outputs a stream of analog samples.

Finite Impulse Response (FIR) filter 106 receives the output signal of the sampler 104. The FIR filter 106 shapes the sampled signal so that it is suitable for input into a data detector 108.

The data detector 108 receives the shaped signal from the FIR 106. The data detector 108 could be a simple threshold detector, but a maximum likelihood sequence detector (i.e. a Viterbi detector) would provide better detection capability.

FIG. 1B is a diagram of a first analog front-end circuit 102 for the first prior art synchronous data detection system 100. The variable gain amplifier (VGA) 120 receives an analog read-back signal containing read-back data and amplifies the signal by an amount determined by a control signal received from the gain control circuit 114. The amplified signal output by the VGA may be input into an (optional) analog equalizer 122. Such an equalizer 122 is a filter which modifies the shape of the signal and is optional because a similar function is performed after sampling by the FIR filter 106.

FIG. 1C is a diagram of a second analog front-end circuit 103, including a high-pass filter 130, for the first prior art synchronous data detection system 100. The high-pass filter 130 receives an analog read-back signal and filters out lower frequency components of the signal before outputting the signal to the VGA 120. Such high-pass filtering reduces the effect of a thermal asperity event on the baseline of the read-back signal but also distorts the read-back signal.

FIG. 1D is a diagram of a high-pass filter 130. The input of the high-pass filter 130 splits into two signal paths. The signal along the first path goes through a low-pass filter 140 and this is subtracted from the signal along the second path in a summation device 142. The output of the summation device 142 is output by the high-pass filter 130.

FIG. 2A is a diagram of a second prior art synchronous detection system 200, including a transient detector 204. The second system 200 is similar to the first system 100, but in the second system 200 the sampled signal output by the sampler 104 is input into the transient detector 204 (in addition to being input into the FIR 106). The transient detector 204 detects the presence of transients, such as thermal asperity events, in the sampled signal and outputs a TA_interval signal which indicates the duration of the transient.

In addition, the second system 200 includes a third analog front-end circuit 202 which receives the TA_interval signal from the transient detector 204. The TA_interval signal controls a bypassable high-pass filter 210 in the third analog front-end circuit 202.

FIG. 2B is a diagram of an analog front-end circuit 202, including a bypassable high-pass filter 210, for the second prior art synchronous detection system 200. The bypassable high-pass filter 210 receives an analog read-back signal and high-pass filters the signal if the TA_interval signal received from the transient detector 204 indicates to do so based on the presence of a transient. The output of the bypassable high-pass filter is received by the VGA 120.

FIG. 2C is a diagram of a bypassable high-pass filter 210. The input of the bypassable high-pass filter 210 splits into two signal paths. The signal along the first path goes through a high-pass filter 130 before going into the first input (1) of a 2:1 multiplexer (MUX) 215. The signal along the second path goes into the second input (0) of the 2:1 MUX 215. The selection input (S) for the 2:1 MUX 215 is the TA_interval signal received from the transient detector 204 such that the first input (1) is output during the transient interval and the second input (0) is output otherwise.

FIG. 2D is a diagram of a transient detector 204. In conjunction with FIG. 2D, FIG. 2E shows illustrative graphs of various signals in the transient detector 204.

A low-pass filter 220 receives the sampled signal x from the sampler 104. A sampled signal x is shown for purposes of illustration in FIG. 2E. (Note that in actuality the signal x and subsequent signals should be sampled rather than continuous as shown in the illustration.) The “oscillations” in the illustration indicate the read-back data cells in the signal x. Near the time of a TA event, the signal x spikes up, and it is several cells before the effect of the TA event fades away from the signal x.

The low-pass filter 220 removes the higher frequency components from the signal x and outputs a low-pass filter y. The low-pass signal y is shown for purposes of illustration in FIG. 2E. As shown in the illustration, the read-back data information is generally removed by the low-pass filtering, leaving only the effect on the signal from the TA event.

The threshold detector 222 receives the low-pass signal y and outputs a threshold signal z. The threshold signal is shown for purposes of illustration in FIG. 2E. As shown in the illustration, the threshold signal z is low if the low-pass signal y is below a predetermined threshold, and is high if the low-pass signal is above the predetermined threshold.

The pulse widener 224 receives the threshold signal z and outputs a “thermal asperity interval” (TA_interval) signal. The TA_interval signal is shown for purposes of illustration in FIG. 2E. As shown in the illustration, the TA_interval begins low like the threshold signal z, goes high when the threshold signal z becomes high, but does not go back low until substantially after the threshold signal z goes back low. The purpose of this widening of the pulse is to allow enough time for the transient produced by the TA event to decay to an amplitude sufficiently small in comparison to the amplitude of the normal read-back date signal (i.e., the amplitude of the “oscillations” in the sampled signal x).

FIG. 3A is a diagram of a third synchronous data detection system 300, including a high-pass filter 130, in a first and alternate embodiment of the present invention. In conjunction with FIG. 3A, FIG. 3B shows illustrative graphs of the input and output of the high-pass filter 130 in the third synchronous data detection system 300.

The third system 300 adds to the first system 100 a strategically placed high-pass filter 130. The high-pass filter 130 receives the shaped signal from the FIR filter 106, and outputs a high-pass signal to the timing control circuit 110 and to the gain control circuit 114. As illustrated in FIG. 3B, the effect of the TA event is present in the shaped signal but is substantially removed from the high-pass signal.

The removal of the effect of the transient from the signal entering the timing 110 and gain 114 control circuits facilitates the tracking of the timing and gain variations in the read-back signal. If the effect of the transient is not removed from the signal, then the effect of the transient throws off the phase-locked loop (PLL) of the timing control circuit 110 and the gain adjustment scheme of the gain control circuit 114.

FIG. 4 is a diagram of a fourth synchronous data detection system 400, including a bypassable high-pass filter 210, in a second and preferred embodiment of the present invention. The fourth system 400 adds to the first system 100 a transient detector 204 and a strategically placed bypassable high-pass filter 210. The transient detector 204 receives the sampled signal from the sampler 104 and outputs a TA_interval signal which indicates when the read-back signal is affected by a transient. The bypassable high-pass filter 210 receives the shaped signal from the FIR 106 and sends its output to the timing 110 and gain 114 control circuits. The TA_interval signal controls the bypassable high-pass filter 210 such that the high-pass filtering is switched on (i.e., the first input (1) is selected by MUX 215 in FIG. 2C) during the time when there is substantial effect by the transient in the read-back signal (i.e., when the TA_interval signal is high).

In this way, switching on the high-pass filtering substantially removes the effect of the transient from the signal entering the timing 110 and gain 114 control circuits. This facilitates the tracking of the timing and gain variations during the transient interval.

FIG. 5 is a diagram of a fifth synchronous data detection system 500 in a third and alternate embodiment of the present invention. The fifth system 500 includes an analog front-end 202 that is different from the analog front-end 102 or 130 in the fourth system 400. The analog front-end circuit 202 of the fifth system 500 includes a bypassable high-pass filter 210 (see FIG. 2B) that is controlled by the TA_interval signal from the transient detector 204.

The fifth system 500 thus includes two bypassable high-pass filters 210: one in the analog front-end and the other before the timing 110 and gain 114 controls. Both bypassable high-pass filters 210 have their high-pass filtering switched on during the transient interval (i.e., when the TA_interval is high). The addition of the high pass filtering in the analog front-end 202 substantially removes the effect of the transient on the read-back signal but also distorts the read-back signal.

The above description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention. The scope of the invention is to be limited only by the following claims. From the above discussion, many variations will be apparent to one skilled in the art that would yet be encompassed by the spirit and scope of the invention.

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Reference
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7274523 *Mar 31, 2004Sep 25, 2007Stmicroelectronics, Inc.Read head preamplifier with thermal asperity transient control
US7436921 *Nov 5, 2004Oct 14, 2008Rockwell Collins, Inc.Frequency sampling phase detector
US8742962 *Oct 25, 2012Jun 3, 2014Renesas Electronics CorporationSemiconductor device and sensor system
US20050219725 *Mar 31, 2004Oct 6, 2005Kemal OzanogluRead head preamplifier with thermal asperity transient control
US20130120178 *May 16, 2013Renesas Electronics CorporationSemiconductor device and sensor system
Classifications
U.S. Classification327/100, 375/345, 327/155, 375/376, 327/559
International ClassificationG11B20/14, G11B20/10
Cooperative ClassificationG11B20/10009, G11B20/1403, G11B20/10055
European ClassificationG11B20/10A6A, G11B20/10A, G11B20/14A
Legal Events
DateCodeEventDescription
Feb 2, 2001ASAssignment
Owner name: MARVELL INTERNATIONAL LTD., BERMUDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL TECHNOLOGY GROUP, LTD.;REEL/FRAME:011514/0674
Effective date: 20010119
Jun 18, 2002SULPSurcharge for late payment
Jun 18, 2002FPAYFee payment
Year of fee payment: 4
May 3, 2006FPAYFee payment
Year of fee payment: 8
May 3, 2010FPAYFee payment
Year of fee payment: 12