|Publication number||USRE37769 E1|
|Application number||US 08/316,035|
|Publication date||Jun 25, 2002|
|Filing date||Sep 29, 1994|
|Priority date||Apr 30, 1990|
|Also published as||DE69130622D1, DE69130622T2, EP0455339A2, EP0455339A3, EP0455339B1, US5151387, US5279887|
|Publication number||08316035, 316035, US RE37769 E1, US RE37769E1, US-E1-RE37769, USRE37769 E1, USRE37769E1|
|Inventors||James Brady, Tsiu Chiu Chan, David Scott Culver|
|Original Assignee||Stmicroelectronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (47), Non-Patent Citations (15), Classifications (17), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention is related generally to integrated circuits, and more specifically to a contact between different layers of polycrystalline silicon interconnect.
2. Description of the Prior Art
In semiconductor circuits, it is known that ohmic contacts are desirable between interconnect layers. An ohmic contact is one in which no P-N junction is formed.
When polycrystalline silicon interconnect lines having different conductivity types make contact, a P-N junction is formed. A similar junction can be formed when polycrystalline silicon having the same conductivity type, but very different doping levels (such as N−− to N +) make contact. For various reasons, it is often desirable to have interconnect having different conductivity types make contact, and it would be desirable to provide an ohmic contact for such structures.
It is therefore an object of the present invention to provide an ohmic contact between polycrystalline silicon interconnect layers having different conductivity types.
It is another object of the present invention to provide such a contact which is easily formed with a process compatible with existing process technologies.
It is a further object of the present invention to provide such a contact which is suitable for use in an SRAM structure to provide a load.
Therefore, according to the present invention, a contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes the ohmic contact with the silicided region of the lower polycrystalline silicon layer.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIGS. 1-3 illustrate a preferred method for forming a contact according to the present invention; and
FIG. 4 is a schematic diagram of the SRAM cell utilizing an ohmic contact formed according to the present invention.
The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.
Referring to FIG. 1, a semiconductor substrate 10 is partially covered with an oxide layer 12. The oxide layer 12 is not complete over the entire surface of the substrate 10, but that portion of interest to the present description has no openings to the substrate 10.
A polycrystalline silicon layer 14 lies on the oxide layer 12. In the illustrative embodiment, layer 14 is doped N-type. The polycrystalline silicon layer 14 has been silicided to form a silicide layer 16 thereon. The polycrystalline silicon 14 and silicide layer 16 have been patterned in a previous processing step as known in the art to form a signal line. The polycrystalline silicon layer 14 may be a first polycrystalline silicon layer, such as commonly used to form gate electrodes of field effect devices. Alternatively, polycrystalline silicon layer 14 may be a second or later level used for interconnect between different portions of an integrated circuit device. At the processing stage shown in FIG. 1, the transistors of the device have already been formed.
Once the polycrystalline silicon and silicide layers 14, 16 have been formed and patterned, an oxide layer 18 is formed over the surface of the device. Oxide layer 18 is typically a thin oxide layer, having a thickness of between 500 and 1000 angstroms. The thickness of oxide layer 18 may be any thickness which is compatible with the fabrication process with which the invention described herein is being used.
Referring to FIG. 2, oxide layer 18 is patterned and etched to define a contact opening 20 to the upper surface of the silicide layer 16. A layer of polycrystalline silicon 22 is then deposited over the surface of the device.
A light dosage of boron is implanted into the polycrystalline silicon layer 22 in order to convert it to a P-type conductor. A typical dosage would be approximately 1013 atoms/cm2.
Referring to FIG. 3, the polycrystalline silicon layer 22 is then masked, and a heavy arsenic implant made to define an N+region 24. A typical dosage for such implant is 5×1015 atoms/cm2. Such doping level is used to allow the N+region 24 to be used as a power supply line.
A P-N junction 26 is formed at the interface between the N+region 24 and the lightly P-doped polycrystalline silicon layer 22. The doping of polycrystalline silicon layer 22 is low enough to define a resistor, but is sufficiently high to cause degeneration in the contact opening 20, providing an ohmic contact between the polycrystalline silicon layer 22 and the silicide layer 16. Thus, although the polycrystalline silicon layer 14 is N-type, no P-N junction is formed at the contact between the two layers 14, 22.
After formation of the highly doped N+regions 24, the polycrystalline silicon layer 22 is etched to define interconnect, leaving the structure shown in FIG. 3. The device is then ready for formation of further oxide and interconnect levels as desired.
Referring to FIG. 4, a 4-transistor SRAM cell is shown. The contact structure formed in FIG. 1-3 is suitable for use as a load element in the cell of FIG. 4.
Cross-coupled field effect devices 30, 32 form the basis of the SRAM cell. Access transistors 34, 36 connect the bit line BL and complemented bit line BL′ to common nodes 38, 40, respectively. Access transistors 34, 36 are driven by the word line 42 as known in the art. Node 38 is connected to the power supply line Vcc through resistor 44 and diode 46. Node 40 is connected to Vcc through resistor 48 and diode 50.
Node 38 corresponds to contact opening 20 in FIG. 3. Resistor 44 corresponds to polycrystalline silicon region 22 of FIG. 3, with diode 46 being formed at the junction 26. Node 40, resistor 48, and diode 50 correspond to FIG. 3 in a similar manner.
Since the contact at contact opening 20, corresponding to nodes 38 and 40, is an ohmic contact, the load for the SRAM cell is formed by a resistor and a diode rather than back-to-back polycrystalline silicon diodes. In some SRAM cell designs, this can provide improved performance over the use of a resistor alone, or back-to-back polycrystalline silicon diodes.
A similar ohmic contact can be formed between a lower polycrystalline silicon layer which is doped P-type and an upper N-type layer. The silicide layer prevents formation of a P-N junction in the contact opening.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4178674||Mar 27, 1978||Dec 18, 1979||Intel Corporation||Process for forming a contact region between layers of polysilicon with an integral polysilicon resistor|
|US4180826||May 19, 1978||Dec 25, 1979||Intel Corporation||MOS double polysilicon read-only memory and cell|
|US4214917||Feb 10, 1978||Jul 29, 1980||Emm Semi||Process of forming a semiconductor memory cell with continuous polysilicon run circuit elements|
|US4290185||May 29, 1979||Sep 22, 1981||Mostek Corporation||Method of making an extremely low current load device for integrated circuit|
|US4322821 *||Dec 19, 1979||Mar 30, 1982||U.S. Philips Corporation||Memory cell for a static memory and static memory comprising such a cell|
|US4367580||Mar 21, 1980||Jan 11, 1983||Texas Instruments Incorporated||Process for making polysilicon resistors|
|US4370798||Jul 20, 1981||Feb 1, 1983||Texas Instruments Incorporated||Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon|
|US4398335 *||Dec 9, 1980||Aug 16, 1983||Fairchild Camera & Instrument Corporation||Multilayer metal silicide interconnections for integrated circuits|
|US4505026||Jul 14, 1983||Mar 19, 1985||Intel Corporation||CMOS Process for fabricating integrated circuits, particularly dynamic memory cells|
|US4535427||Dec 6, 1982||Aug 13, 1985||Mostek Corporation||Control of serial memory|
|US4554729||Jan 22, 1982||Nov 26, 1985||Hitachi, Ltd.||Method of making semiconductor memory device|
|US4560419||May 30, 1984||Dec 24, 1985||Inmos Corporation||Method of making polysilicon resistors with a low thermal activation energy|
|US4561907||Jul 12, 1984||Dec 31, 1985||Bruha Raicu||Process for forming low sheet resistance polysilicon having anisotropic etch characteristics|
|US4562640 *||Mar 22, 1984||Jan 7, 1986||Siemens Aktiengesellschaft||Method of manufacturing stable, low resistance contacts in integrated semiconductor circuits|
|US4581623 *||May 24, 1984||Apr 8, 1986||Motorola, Inc.||Interlayer contact for use in a static RAM cell|
|US4617071 *||Oct 27, 1981||Oct 14, 1986||Fairchild Semiconductor Corporation||Method of fabricating electrically connected regions of opposite conductivity type in a semiconductor structure|
|US4619037||Nov 19, 1985||Oct 28, 1986||Kabushiki Kaisha Toshiba||Method of manufacturing a semiconductor device|
|US4654824 *||Dec 18, 1984||Mar 31, 1987||Advanced Micro Devices, Inc.||Emitter coupled logic bipolar memory cell|
|US4658378||Dec 15, 1982||Apr 14, 1987||Inmos Corporation||Polysilicon resistor with low thermal activation energy|
|US4675715 *||Oct 7, 1985||Jun 23, 1987||American Telephone And Telegraph Company, At&T Bell Laboratories||Semiconductor integrated circuit vertical geometry impedance element|
|US4677735 *||Jan 9, 1986||Jul 7, 1987||Texas Instruments Incorporated||Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer|
|US4714685 *||Dec 8, 1986||Dec 22, 1987||General Motors Corporation||Method of fabricating self-aligned silicon-on-insulator like devices|
|US4792923 *||Aug 29, 1986||Dec 20, 1988||Mitsubishi Denki Kabushiki Kaisha||Bipolar semiconductor memory device with double word lines structure|
|US4804636 *||Mar 7, 1986||Feb 14, 1989||Texas Instruments Incorporated||Process for making integrated circuits having titanium nitride triple interconnect|
|US4831424 *||Jun 15, 1987||May 16, 1989||Hitachi, Ltd.||Insulated gate semiconductor device with back-to-back diodes|
|US4849344 *||Oct 27, 1988||Jul 18, 1989||Fairchild Semiconductor Corporation||Enhanced density modified isoplanar process|
|US4870033 *||Mar 3, 1987||Sep 26, 1989||Yamaha Corporation||Method of manufacturing a multilayer electrode containing silicide for a semiconductor device|
|US4874719 *||Jul 18, 1988||Oct 17, 1989||Kabushiki Kaisha Toshiba||Method for manufacturing an electrical connection between conductor levels|
|US4877483||Jun 29, 1988||Oct 31, 1989||S.G.S. Thomson Microelectronics, S.A.||Method for contact between two conductive or semi-conductive layers deposited on a substrate|
|US4903096||Oct 25, 1988||Feb 20, 1990||Kabushiki Kaisha Toshiba||Semiconductor memory device with barrier layer|
|US4907052||Jan 23, 1989||Mar 6, 1990||Kanegafuchi Kagaku Kogyo Kabushiki Kaisha||Semiconductor tandem solar cells with metal silicide barrier|
|US4922455||Sep 8, 1987||May 1, 1990||International Business Machines Corporation||Memory cell with active device for saturation capacitance discharge prior to writing|
|US4933735 *||Jul 27, 1984||Jun 12, 1990||Unisys Corporation||Digital computer having control and arithmetic sections stacked above semiconductor substrate|
|US4948747 *||Dec 18, 1989||Aug 14, 1990||Motorola, Inc.||Method of making an integrated circuit resistor|
|US4950620||Sep 30, 1988||Aug 21, 1990||Dallas Semiconductor Corp.||Process for making integrated circuit with doped silicon dioxide load elements|
|US4966864||Mar 27, 1989||Oct 30, 1990||Motorola, Inc.||Contact structure and method|
|US4968645||Dec 15, 1988||Nov 6, 1990||Sgs-Thomson Microelectronics S.R.L.||Method for manufacturing MOS/CMOS monolithic integrated circuits including silicide and polysilicon patterning|
|US5021849||Oct 30, 1989||Jun 4, 1991||Motorola, Inc.||Compact SRAM cell with polycrystalline silicon diode load|
|US5107322||Sep 22, 1989||Apr 21, 1992||Seiko Epson Corporation||Wiring or conductor interconnect for a semiconductor device or the like|
|US5151376||May 31, 1990||Sep 29, 1992||Sgs-Thomson Microelectronics, Inc.||Method of making polycrystalline silicon resistors for integrated circuits|
|US5187114||Jun 3, 1991||Feb 16, 1993||Sgs-Thomson Microelectronics, Inc.||Method of making SRAM cell and structure with polycrystalline P-channel load devices|
|US5196233||Jan 18, 1989||Mar 23, 1993||Sgs-Thomson Microelectronics, Inc.||Method for fabricating semiconductor circuits|
|EP0182610A2||Nov 14, 1985||May 28, 1986||Fujitsu Limited||Semiconductor photodetector device|
|JP6068634B2||Title not available|
|JPS6068634A||Title not available|
|JPS6298660A||Title not available|
|JPS58135653A||Title not available|
|1||1989 Symposium on VLSI Technology, Digest of Technical Papers, pp. 61-62, May 22-25, "A New Process Technology for a 4Mbit SRAM with Polysilicon Load Resistor Cell", Yuzuriha et al.|
|2||IEEE GaAs IC Symposium, 1984, Hayashi et al., "ECL-Compatible GaAs SRAM Circuit Technology for High Performance Computer Application", pp. 111-114.|
|3||IEEE J of Solid State Cir., vol. 18. No. 5, Oct. 1983, "A 4.5 ns Access Time 1K×4 Bit ECL RAM", Nakubo et al., pp. 515-520.|
|4||IEEE J of Solid State Cir., vol. 18. No. 5, Oct. 1983, "A 4.5 ns Access Time 1Kx4 Bit ECL RAM", Nakubo et al., pp. 515-520.|
|5||IEEE J. of Solid State Cir, vol. 21, No. 5, Oct. 1986, "A 1.0-ns 5-Kbit ECL RAM", Chuang et al., pp. 670-674.|
|6||IEEE J. of Solid State Cir, vol. 24, No. 2, Apr. 1989, "A Bipolar ECL Static RAM Using Polysilicon Diode Loaded Memory Cell", Hwang et al., pp. 504-511.|
|7||IEEE Trans Electron Dev., vol. 40. No. 2, Feb. 1993, "Experimental Characterization of the Diode-Type Polysilicon Loads for CMOS SRAM", Kalnitsky et al., pp. 358-363.|
|8||IEEE Trans. Electron Dev. vol. 32, No. 9, Sept. 1985, "Ion-Implanted Thin Polycrystalline High-Value Resistors for High-Density Poly-Load Static RAM Applications", Ohzone et al.|
|9||IEEE Trans. Electron Dev., vol. 30, No. 1, Jan. 1993, "Gigaohm-Range Polycrystalline Silicon Resistors for Microelectronic Appn", Mohan et al., pp. 45-51.|
|10||Physics of Semiconductors, S.M. Sze, 1981, pp. 304-305.|
|11||Silicon Processing for the VLSI Era, vol. 2-Process Integration, pp. 84-85, 176-177, x-xv, 1986, Wolf.|
|12||Solid State Elect, vol. 30, No. 3, pp. 339-343, 1987, "Characterization of Aluminum/LPCVD Polysilicon Schottky Barrier Diodes", Chen et al.|
|13||Solid State Elect., vol. 28 No. 12, pgs. 1255-1261 1985 "Field Enhanged Emission and Capture in Polysilicon pn Junctions", Greve et al.|
|14||Solid State Electronics, vol. 15, pp. 1103-1106, 1972, "P-N junctions in Polycrystalline Silicon Films," Manoliu et al.|
|15||*||Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, Calif. (1990), Chapters 3&4.*|
|U.S. Classification||438/385, 438/625, 438/647, 438/532|
|International Classification||H01L21/768, H01L21/3205, H01L23/52, H01L23/522, H01L23/532|
|Cooperative Classification||Y10T428/24926, Y10T428/24917, H01L2924/0002, Y10S148/019, H01L23/53271, H01L23/5226|
|European Classification||H01L23/522E, H01L23/532M2|
|Apr 18, 2002||AS||Assignment|
Owner name: STMICROELECTRONICS, INC., TEXAS
Free format text: CHANGE OF NAME;ASSIGNOR:SGS-THOMSON MICROELECTRONICS, INC.;REEL/FRAME:012842/0463
Effective date: 19980519
|Dec 10, 2003||FPAY||Fee payment|
Year of fee payment: 12